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1. general description the SAA7108AE; saa7109ae is a new multistandard video decoder and encoder chip, offering high quality video input and tv output processing as required by pc-99 speci?cations. it enables hardware manufacturers to implement versatile video functions on a signi?cantly reduced printed-circuit board area at very competitive costs. separate pins for supply voltages as well as for i 2 c-bus control and boundary scan test have been provided for the video encoder and decoder sections to ensure both ?exible handling and optimized noise behavior. the video encoder is used to encode pc graphics data at maximum 1280 1024 resolution (optionally 1920 1080 interlaced) to pal (50 hz) or ntsc (60 hz) video signals. a programmable scaler and anti-?icker ?lter (maximum 5 lines) ensures properly sized and ?icker-free tv display as cvbs or s-video output. alternatively, the three digital-to-analog converters (dacs) can output rgb signals together with a ttl composite sync to feed scart connectors. when the scaler/interlacer is bypassed, a second vga monitor can be connected to the rgb outputs and separate h and v-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 1024 resolution/60 hz (pixclk < 85 mhz). alternatively this port can provide y, p b and p r signals for hdtv monitors. the encoder section includes a sync/clock generator and on-chip dacs. all inputs intended to interface to the host graphics controller are designed for low-voltage signals down to 1.1 v and up to 3.45 v. the video decoder , a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing ?lter and analog-to-digital converter (adc), automatic clamp and gain control, a clock generation circuit (cgc), and a digital multistandard decoder (pal bghi, pal m, pal n, combination pal n, ntsc m, ntsc-japan, ntsc n, ntsc 4.43 and secam). the decoder includes a brightness, contrast and saturation control circuit, a multistandard vbi data slicer and a 27 mhz vbi data bypass. the pure 3.3 v (5 v compatible) cmos circuit SAA7108AE; saa7109ae, consisting of an analog front-end and digital video decoder, a digital video encoder and analog back-end, is a highly integrated circuit especially designed for desktop video applications. the decoder is based on the principle of line-locked clock decoding and is able to decode the color of pal, secam and ntsc signals into itu-r bt.601 compatible color component values. SAA7108AE; saa7109ae hd-codec rev. 03 6 february 2007 product data sheet
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 2 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock. as an option, it is possible to slave the video pal/ntsc encoding to the video decoder clock with the encoder fifo acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock. 2. features 2.1 video decoder n six analog inputs, internal analog source selectors, e.g. 6 cvbs or (2 y/c and 2 cvbs) or (1 y/c and 4 cvbs) n two analog preprocessing channels in differential cmos style for best s/n performance n fully programmable static gain or automatic gain control (agc) for the selected cvbs or y/c channel n switchable white peak control n two built-in analog anti-aliasing ?lters n two 9-bit video cmos analog-to-digital converters (adcs), digitized cvbs or y/c signals are available on the image port data (ipd) port under i 2 c-bus control n on-chip clock generator n line-locked system clock frequencies n digital pll for horizontal sync processing and clock generation, horizontal and vertical sync detection n requires only one crystal (either 24.576 mhz or 32.11 mhz) for all standards n automatic detection of 50 hz and 60 hz ?eld frequency, and automatic switching between pal and ntsc standards n luminance and chrominance signal processing for pal bghi, pal n, combination pal n, pal m, ntsc m, ntsc-japan, ntsc n, ntsc 4.43 and secam n user programmable luminance peaking or aperture correction n cross-color reduction for ntsc by chrominance comb ?ltering n pal delay line for correcting pal phase errors n brightness contrast saturation (bcs) and hue control on-chip n two multifunctional real-time output pins controlled by the i 2 c-bus n multistandard vbi data slicer decoding world standard teletext (wst), north-american broadcast text system (nabts), closed caption (cc), wide screen signalling (wss), video programming system (vps), vertical interval time code (vitc) variants (ebu/smpte) etc. n standard itu 656 y-c b -c r 4 : 2 : 2 format (8-bit) on ipd output bus n enhanced itu 656 output format on ipd output bus containing: u active video u raw cvbs data for intercast applications (27 mhz data rate) u decoded vbi data n detection of copy protected input signals according to the macrovision standard. can be used to prevent unauthorized recording of pay-tv or video tape signals
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 3 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 2.2 video scaler n both up and downscaling n conversion to square pixel format n ntsc to 288 lines (video phone) n phase accuracy better than 1 64 pixel or line, horizontally or vertically n independent scaling de?nitions for odd and even ?elds n anti-alias ?lter for horizontal scaling n provides output as: u scaled active video u raw cvbs data for intercast, wave-phore, popcon applications or general vbi data decoding (27 mhz or sample rate converted) n local video output for y-c b -c r 4:2:2 for mat (vmi, vip and zv) 2.3 video encoder n digital pal/ntsc encoder with integrated high quality scaler and anti-?icker ?lter for tv output from a pc n supports intel digital video out (dvo) low-voltage interfacing to graphics controller n 27 mhz crystal-stable subcarrier generation n maximum graphics pixel clock 85 mhz at double edged clocking, synthesized on-chip or from external source n programmable assignment of clock edge to bytes (in double edged mode) n synthesizable pixel clock (pixclk) with minimized output jitter, can be used as reference clock for the vgc, as well n pixclk output and bi-phase pixclk input (vgc clock loop-through possible) n hot-plug detection through dedicated interrupt pin n supported vga resolutions for pal or ntsc legacy video output up to 1280 1024 graphics data at 60 hz or 50 hz frame rate n supported vga resolutions for hdtv output up to 1920 1080 interlaced graphics data at 60 hz or 50 hz frame rate n three digital-to-analog converters (dacs) for cvbs (blue, c b ), vbs (green, cvbs) and c (red, c r ) at 27 mhz sample rate (signals in parenthesis are optionally selected), all at 10-bit resolution n non-interlaced c b -y-c r or rgb input at maximum 4 : 4 : 4 sampling n downscaling and upscaling from 50 % to 400 % n optional interlaced c b -y-c r input of digital versatile disk (dvd) signals n optional non-interlaced rgb output to drive second vga monitor (bypass mode, maximum 85 mhz) n 3 256 bytes rgb look-up table (lut) n support for hardware cursor n hdtv up to 1920 1080 interlaced and 1280 720 progressive, including 3-level sync pulses n programmable border color of underscan area n programmable 5-line anti-?icker ?lter n on-chip 27 mhz crystal oscillator (3rd harmonic or fundamental 27 mhz crystal) n fast i 2 c-bus control port (400 khz)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 4 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec n encoder can be master or slave n adjustable output levels for the dacs n programmable horizontal and vertical input synchronization phase n programmable horizontal sync output phase n internal color bar generator (cbg) n optional support of various vertical blanking interval (vbi) data insertion n macrovision pay-per-view copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to the SAA7108AE only. 2.4 common features n 5 v tolerant digital inputs and i/o ports n i 2 c-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbit/s) n versatile power-save modes n boundary scan test circuit complies with the ieee std. 1149.b1-1994 (separate id codes for decoder and encoder) n lbga156 package n moisture sensitive level (msl): e3 3. applications n notebook (low-power consumption) n pcmcia card application n agp based graphics cards n pc editing n image processing n video phone applications n intercast and pc teletext applications n security applications n hybrid satellite set-top boxes 4. quick reference data [1] power dissipation is extremely dependent on programming and selected application. table 1. quick reference data symbol parameter conditions min typ max unit v ddd digital supply voltage 3.15 3.3 3.45 v v dda analog supply voltage 3.15 3.3 3.45 v t amb ambient temperature 0 - 70 c p a+d analog and digital power dissipation [1] - - 1.7 w
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 5 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 5. ordering information 6. block diagram table 2. ordering information type number package name description version SAA7108AE lbga156 plastic low pro?le ball grid array package; 156 balls; body 15 15 1.05 mm sot700-1 saa7109ae fig 1. simpli?ed block diagram analog video acquisition and demodulator scaler video decoder part video encoder part x port i port (ipd) digital video input and output scaler and interlacer video encoder cvbs, y/c y-c b -c r /rgb pd analog video input digital video graphics input digital video output cvbs, y/c rgb analog video output mhb903
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 7 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec (1) the pins rtco and alrclk are used for con?guration of the i 2 c-bus interface and the de?nition of the crystal oscillator frequency at reset (pin strapping). fig 3. block diagram (video decoder part) fir-prefilter prescaler and scaler bcs general purpose vbi data slicer video/text arbiter text fifo video fifo programming register array a/b register mux event controller image port pin mapping x port i/o formatting expansion port pin mapping i/o control i 2 c-bus real-time output llc p8 ai2d line fifo buffer vertical scaling horizontal fine (phase) scaling 32 to 8(16) mux g14 itri n10 agnd p12 ai1d m10 aout p6 ai24 p7 ai23 p9 ai22 p10 ai21 p11 ai12 p13 ai11 p3 xtalod p2 xtalid p4 xtoutd n14 ce m12 m14 n4 tckd m6 tmsd m5 tdid n6 v ddxd l8 v ssxd p5 v ddid d11, f11, j4, j11, l4, l11 v dded d10, g11, l7, l9 v ddad m8, m9, n11 v ssid e11, k4, k11 v ssed h4, h11, l6, m13 v ssad m7, n7 to n9, n12, n13 amxclk j12 tdod n5 amclk k12 alrclk j13 asclk k14 llc2 l14 rtco l13 rts0 k13 rts1 l10 xclk m3 xdq m4 k2, k3, l1 to l3, m1, m2, n1 xrh n2 xrv l5 xrdy n3 sdad l12 scld m11 test5 j2 test4 j1 test3 j3 test2 c10 test1 b10 test0 h13 a13, d12, c12, b12, a12, c11, b11, a11 xtri k1 chrominance of 16-bit input boundary scan test clock generation and power-on control analog dual adc digital decoder with adaptive comb filter audio clock generation j14 itrdy h12 iclk g13 igp1 f14 igp0 f13 igpv g12 igph h14 idq e14, d14, c14, b14, e13, d13, c13, b13 ipd [ 7:0 ] hpd [ 7:0 ] xpd [ 7:0 ] resd SAA7108AE saa7109ae trstd (1) (1) mbl791
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 8 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 7. pinning information 7.1 pinning fig 4. pin con?guration (lbga156) 001aae257 SAA7108AE saa7109ae transparent top view p n m l k j g e h f d c b a 246810121314 1357911 ball a1 index area
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SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 10 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 3. pin allocation table pin symbol pin symbol pin symbol pin symbol a2 pd7 a3 pd4 a4 trst e a5 xtalie a6 xtaloe a7 dump a8 v ssxe a9 rset a10 v ddae a11 hpd0 a12 hpd3 a13 hpd7 b1 pd9 b2 pd8 b3 pd5 b4 pd6 b5 tdie b6 v ddae b7 dump b8 v ssae b9 v ddae b10 test1 b11 hpd1 b12 hpd4 b13 ipd0 b14 ipd4 c1 pd11 c2 pd10 c3 ttx_sres c4 ttxrq_xclko2 c5 v ssie c6 blue_cb_cvbs c7 green_vbs_cvbs c8 red_cr_c_cvbs c9 v ddae c10 test2 c11 hpd2 c12 hpd5 c13 ipd1 c14 ipd5 d1 tdoe d2 rese d3 tmse d4 v ddiee d5 v ssie d6 v ddxe d7 vsm d8 hsm_csync d9 v ddae d10 v dded d11 v ddid d12 hpd6 d13 ipd2 d14 ipd6 e1 tcke e2 scle e3 hsvgc e4 v ssee e11 v ssid e12 n.c. e13 ipd3 e14 ipd7 f1 vsvgc f2 pixclki f3 pd3 f4 v dd(dvo) f11 v ddid f12 tvd f13 igpv f14 igp0 g1 fsvgc g2 sdae g3 cbo g4 pixclko g11 v dded g12 igph g13 igp1 g14 itri h1 pd2 h2 pd1 h3 pd0 h4 v ssed h11 v ssed h12 iclk h13 test0 h14 idq j1 test4 j2 test5 j3 test3 j4 v ddid j11 v ddid j12 amxclk j13 alrclk j14 itrdy k1 xtri k2 xpd7 k3 xpd6 k4 v ssid k11 v ssid k12 amclk k13 rts0 k14 asclk l1 xpd5 l2 xpd4 l3 xpd3 l4 v ddid l5 xrv l6 v ssed l7 v dded l8 v ddxd l9 v dded l10 rts1 l11 v ddid l12 sdad l13 rtco l14 llc2 m1 xpd2 m2 xpd1 m3 xclk m4 xdq m5 tmsd m6 tckd m7 v ssad m8 v ddad m9 v ddad m10 aout m11 scld m12 resd m13 v ssed m14 llc n1 xpd0 n2 xrh n3 xrdy n4 trstd n5 tdod n6 tdid n7 v ssad n8 v ssad n9 v ssad n10 agnd n11 v ddad n12 v ssad n13 v ssad n14 ce
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 11 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 7.2 pin description p2 xtalid p3 xtalod p4 xtoutd p5 v ssxd p6 ai24 p7 ai23 p8 ai2d p9 ai22 p10 ai21 p11 ai12 p12 ai1d p13 ai11 table 3. pin allocation table continued pin symbol pin symbol pin symbol pin symbol table 4. pin description symbol pin type [1] description pd7 a2 i msb of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment pd4 a3 i msb - 3 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment trst e a4 i/pu test reset input for boundary scan test (bst) (encoder); active low; with internal pull-up [2] [3] xtalie a5 i 27 mhz crystal input (encoder) xtaloe a6 o 27 mhz crystal output (encoder) dump a7 o dac reference pin (encoder); 12 w resistor connected to v ssae v ssxe a8 s ground for oscillator (encoder) rset a9 o dac reference pin (encoder); 1 k w resistor connected to v ssae v ddae a10 s 3.3 v analog supply voltage (encoder) hpd0 a11 i/o msb - 7 of host port data (hpd) output bus hpd3 a12 i/o msb - 4 of hpd output bus hpd7 a13 i/o msb of hpd output bus pd9 b1 i see t ab le 12 , t ab le 17 and t ab le 18 for pin assignment with different encoder input formats pd8 b2 i see t ab le 12 , t ab le 17 and t ab le 18 for pin assignment with different encoder input formats pd5 b3 i msb - 2 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment pd6 b4 i msb - 1 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment tdie b5 i/pu test data input for bst (encoder) [4] v ddae b6 s 3.3 v analog supply voltage (encoder) dump b7 o dac reference pin (encoder); connected to a7 v ssae b8 s analog ground (encoder) v ddae b9 s 3.3 v analog supply voltage (encoder) test1 b10 i scan test input 1; do not connect hpd1 b11 i/o msb - 6 of hpd output bus hpd4 b12 i/o msb - 3 of hpd output bus ipd0 b13 o msb - 7 of ipd output bus ipd4 b14 o msb - 3 of image port data (ipd) output bus pd11 c1 i see t ab le 12 , t ab le 17 and t ab le 18 for pin assignment with different encoder input formats
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 12 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec pd10 c2 i see t ab le 12 , t ab le 17 and t ab le 18 for pin assignment with different encoder input formats ttx_sres c3 i teletext input or sync reset input (encoder) ttxrq_xclko2 c4 o teletext request output or 13.5 mhz clock output of the crystal oscillator (encoder) v ssie c5 s digital ground core (encoder) blue_cb_cvbs c6 o blue or c b or cvbs output green_vbs_cvbs c7 o green or vbs or cvbs output red_cr_c_cvbs c8 o red or c r or c or cvbs output v ddae c9 s 3.3 v analog supply voltage (encoder) test2 c10 i scan test input 2; do not connect hpd2 c11 i/o msb - 5 of hpd output bus hpd5 c12 i/o msb - 2 of hpd output bus ipd1 c13 o msb - 6 of ipd output bus ipd5 c14 o msb - 2 of ipd output bus tdoe d1 o test data output for bst (encoder) [4] rese d2 i reset input (encoder); active low tmse d3 i/pu test mode select input for bst (encoder) [4] v ddiee d4 s 3.3 v digital supply voltage for core and peripheral cells (encoder) v ssie d5 s digital ground core (encoder) v ddxe d6 s 3.3 v supply voltage for oscillator (encoder) vsm d7 o vertical synchronization output to vga monitor (non-interlaced) hsm_csync d8 o horizontal synchronization output to vga monitor (non-interlaced) or composite sync for rgb-scart v ddae d9 s 3.3 v analog supply voltage (encoder) v dded d10 s 3.3 v digital supply voltage for peripheral cells (decoder) v ddid d11 s 3.3 v digital supply voltage for core (decoder) hpd6 d12 i/o msb - 1 of hpd output bus ipd2 d13 o msb - 5 of ipd output bus ipd6 d14 o msb - 1 of ipd output bus tcke e1 i/pu test clock input for bst (encoder) [4] scle e2 i(/o) serial clock input (i 2 c-bus encoder) with inactive output path hsvgc e3 i/o horizontal synchronization output to video graphics controller (vgc) (optional input) v ssee e4 s digital ground peripheral cells (encoder) v ssid e11 s digital ground core (decoder) n.c. e12 - not connected ipd3 e13 o msb - 4 of ipd output bus ipd7 e14 o msb of ipd output bus vsvgc f1 i/o vertical synchronization output to vgc (optional input) pixclki f2 i pixel clock input (looped through) table 4. pin description continued symbol pin type [1] description
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 13 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec pd3 f3 i msb - 4 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment v dd(dvo) f4 s digital supply voltage for dvo cells v ddid f11 s 3.3 v digital supply voltage for core (decoder) tvd f12 o tv detector; hot-plug interrupt pin; high if tv is connected igpv f13 o multi-purpose vertical reference output with ipd output bus igp0 f14 o general purpose output signal 0 with ipd output bus fsvgc g1 i/o frame synchronization output to vgc (optional input) sdae g2 i/o serial data input/output (i 2 c-bus encoder) cbo g3 o composite blanking output to vgc; active low pixclko g4 o pixel clock output to vgc v dded g11 s 3.3 v digital supply voltage for peripheral cells (decoder) igph g12 o multi-purpose horizontal reference output with ipd output bus igp1 g13 o general purpose output signal 1 with ipd output bus itri g14 i(/o) programmable control signals for ipd output bus pd2 h1 i msb - 5 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment pd1 h2 i msb - 6 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment pd0 h3 i msb - 7 of encoder input bus with c b -y-c r 4:2:2;see t ab le 12 to t ab le 18 for pin assignment v ssed h4 s digital ground for peripheral cells (decoder) v ssed h11 s digital ground for peripheral cells (decoder) iclk h12 i/o clock for ipd output bus (optional clock input) test0 h13 o scan test output; do not connect idq h14 o data quali?er for ipd output bus test4 j1 o scan test output; do not connect test5 j2 i scan test input; do not connect test3 j3 i scan test input; do not connect v ddid j4 s 3.3 v digital supply voltage for core (decoder) v ddid j11 s 3.3 v digital supply voltage for core (decoder) amxclk j12 i audio master external clock input alrclk j13 (i/)o audio left/right clock output; can be strapped [5] [6] to supply via a 3.3 k w resistor to indicate that the default 24.576 mhz crystal (pin alrclk = low; internal pull-down) has been replaced by a 32.110 mhz crystal (pin alrclk = high) itrdy j14 i target ready input for ipd output bus xtri k1 i control signal for all x port pins xpd7 k2 i/o msb of xpd bus xpd6 k3 i/o msb - 1 of xpd bus v ssid k4 s digital ground core (decoder) v ssid k11 s digital ground core (decoder) amclk k12 o audio master clock output, must be less than 50 % of crystal clock table 4. pin description continued symbol pin type [1] description
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 14 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec rts0 k13 o real-time status or sync information line 0 asclk k14 o audio serial clock output xpd5 l1 i/o msb - 2 of xpd bus xpd4 l2 i/o msb - 3 of xpd bus xpd3 l3 i/o msb - 4 of xpd bus v ddid l4 s 3.3 v digital supply voltage for core (decoder) xrv l5 i/o vertical reference for xpd bus v ssed l6 s digital ground for peripheral cells (decoder) v dded l7 s 3.3 v digital supply voltage for peripheral cells (decoder) v ddxd l8 s 3.3 v supply voltage for oscillator (decoder) v dded l9 s 3.3 v digital supply voltage for peripheral cells (decoder) rts1 l10 o real-time status or sync information line 1 v ddid l11 s 3.3 v digital supply voltage for core (decoder) sdad l12 i/o serial data input/output (i 2 c-bus decoder) rtco l13 (i/)o real-time control output; contains information about actual system clock frequency, ?eld rate, odd/even sequence, decoder status, subcarrier frequency and phase and pal sequence (see external document how to use real time control (rtc) , available on request); the rtco pin [5] [7] is enabled via i 2 c-bus bit rtce; see t ab le 162 llc2 l14 o line-locked 1 2 clock output (13.5 mhz nominal) xpd2 m1 i/o msb - 5 of xpd bus xpd1 m2 i/o msb - 6 of xpd bus xclk m3 i/o clock for xpd bus xdq m4 i/o data quali?er for xpd bus tmsd m5 i/pu test mode select input for bst (decoder) [4] tckd m6 i/pu test clock input for bst (decoder) [4] v ssad m7 s analog ground (decoder) v ddad m8 s 3.3 v analog supply voltage (decoder) v ddad m9 s 3.3 v analog supply voltage (decoder) aout m10 o do not connect; analog test output scld m11 i(/o) serial clock input (i 2 c-bus decoder) with inactive output path resd m12 o reset output signal; active low (decoder) v ssed m13 s digital ground for peripheral cells (decoder) llc m14 o line-locked clock output (27 mhz nominal) xpd0 n1 i/o msb - 7 of xpd bus xrh n2 i/o horizontal reference for xpd bus xrdy n3 o data input ready for xpd bus trstd n4 i/pu test reset input for bst (decoder); active low; with internal pull-up [2] [3] tdod n5 o test data output for bst (decoder) [4] tdid n6 i/pu test data input for bst (decoder) [4] v ssad n7 s analog ground (decoder) v ssad n8 s analog ground (decoder) table 4. pin description continued symbol pin type [1] description
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 15 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] pin type: i = input, o = output, s = supply, pu = pull-up. [2] for board design without boundary scan implementation connect trst e and trstd to ground. [3] this pin provides easy initialization of the boundary scan test (bst) circuit. trst e and trstd can be used to force the test access port (tap) controller to the test_logic_reset state (normal operation) at once. [4] in accordance with the ieee1149.1 standard the pins tdie (tdid), tmse (tmsd), tcke (tckd) and trst e ( trstd) are input pins with an internal pull-up resistor and tdoe (tdod) is a 3-state output pin. [5] pin strapping is done by connecting the pin to supply via a 3.3 k w resistor. during the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. for the default setting no strapping resistor is necessary (internal pu ll-down). [6] pin alrclk = low for 24.576 mhz crystal (default); pin alrclk = high for 32.110 mhz crystal. [7] pin rtco operates as i 2 c-bus slave address pin; pin rtco = low for slave address 42h/43h (default); pin rtco = high for slave address 40h/41h. 8. functional description of digital video encoder part the digital video encoder part encodes digital luminance and color difference signals (c b -y-c r ) or digital rgb signals into analog cvbs, s-video and, optionally, rgb or c r -y-c b signals. ntsc m, pal b/g and sub-standards are supported. the SAA7108AE; saa7109ae can be directly connected to a pc video graphics controller with a maximum resolution of 1280 1024 (progressive) or 1920 1080 (interlaced) at a 50 hz or 60 hz frame rate. a programmable scaler scales the computer graphics picture so that it will ?t into a standard tv screen with an adjustable underscan area. non-interlaced-to-interlaced conversion is optimized with an adjustable anti-?icker ?lter for a ?icker-free display at a very high sharpness. v ssad n9 s analog ground (decoder) agnd n10 s analog ground (decoder) connected to substrate v ddad n11 s 3.3 v analog supply voltage (decoder) v ssad n12 s analog ground (decoder) v ssad n13 s analog ground (decoder) ce n14 i chip enable or reset input (with internal pull-up) xtalid p2 i 27 mhz crystal input (decoder) xtalod p3 o 27 mhz crystal output (decoder) xtoutd p4 o crystal oscillator output signal (decoder); auxiliary signal v ssxd p5 s ground for crystal oscillator (decoder) ai24 p6 i analog input 24 ai23 p7 i analog input 23 ai2d p8 i differential analog input for channel 2; connect to ground via a capacitor ai22 p9 i analog input 22 ai21 p10 i analog input 21 ai12 p11 i analog input 12 ai1d p12 i differential analog input for channel 1; connect to ground via a capacitor ai11 p13 i analog input 11 table 4. pin description continued symbol pin type [1] description
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 16 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec besides the most common 16-bit 4 :2:2 c b -y-c r input format (using 8 pins with double edge clocking), other c b -y-c r and rgb formats are also supported; see t ab le 12 to t ab le 18 . a complete 3 bytes 256 bytes look-up table (lut), which can be used, for example, as a separate gamma corrector, is located in the rgb domain; it can be loaded either through the video input port pixel data (pd) or via the i 2 c-bus. the SAA7108AE; saa7109ae supports a 32-bit 32-bit 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the i 2 c-bus. it is also possible to encode interlaced 4:2:2 video signals such as pc-dvd; for that the anti-?icker ?lter, and in most cases the scaler, will simply be bypassed. besides the applications for video output, the SAA7108AE; saa7109ae can also be used for generating a kind of auxiliary vga output, when the rgb non-interlaced input signal is fed to the dacs. this may be of interest for example, when the graphics controller provides a second graphics window at its video output port. the basic encoder function consists of subcarrier generation, color modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 mhz (independent of the actual pixel clock used at the input side), corresponding to an internal 4:2:2 bandwidth in the luminance/color difference domain. luminance and chrominance signals are ?ltered in accordance with the standard requirements of rs-170-a and itu-r bt.470-3 . for ease of analog post ?ltering the signals are twice oversampled to 27 mhz before digital-to-analog conversion. the total ?lter transfer characteristics (scaler and anti-?icker ?lter are not taken into account) are illustrated in figure 6 to figure 11 . all three dacs are realized with full 10-bit resolution. the c r -y-c b to rgb dematrix can be bypassed (optionally) in order to provide the upsampled c r -y-c b input signals. the 8-bit multiplexed c b -y-c r formats are itu-r bt.656 (d1 format) compatible, but the sav and eav codes can be decoded optionally, when the device is operated in slave mode. for assignment of the input data to the rising or falling clock edge see t ab le 12 to t ab le 18 . in order to display interlaced rgb signals through a euro-connector tv set, a separate digital composite sync signal (pin hsm_csync) can be generated; it can be advanced up to 31 periods of the 27 mhz crystal clock in order to be adapted to the rgb processing of a tv set. the SAA7108AE; saa7109ae synthesizes all necessary internal signals, color subcarrier frequency and synchronization signals from that clock. wide screen signalling data can be loaded via the i 2 c-bus and is inserted into line 23 for standards using a 50 hz ?eld rate. vps data for program dependent automatic start and stop of such featured vcrs is loadable via the i 2 c-bus.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 17 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the ic also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 mhz clock rate (see figure 66 ). it is also possible to load data for the copy generation management system into line 20 of every ?eld (525/60 line counting). a number of possibilities are provided for setting different video parameters such as: ? black and blanking level control ? color subcarrier frequency ? variable burst amplitude etc. (1) scbw = 1. (2) scbw = 0. fig 6. chrominance transfer characteristic f (mhz) mbe737 - 30 - 18 - 42 - 6 6 0 g v (db) - 54 - 24 - 12 - 36 - 48 0 14 10 12 8 246 (1) (2)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 18 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec (1) scbw = 1. (2) scbw = 0. fig 7. chrominance transfer characteristic (enlargement of figure 6 ) (1) ccrs[1:0] = 01. (2) ccrs[1:0] = 10. (3) ccrs[1:0] = 11. (4) ccrs[1:0] = 00. fig 8. luminance transfer characteristic (excluding scaler) 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 1.2 f (mhz) g v (db) (1) (2) mbe735 f (mhz) mgd672 - 30 - 18 - 42 - 6 6 0 g v (db) - 54 0 14 10 12 8 246 (1) (2) (4) (3) - 24 - 12 - 36 - 48
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 19 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec (1) ccrs[1:0] = 00. fig 9. luminance transfer characteristic (excluding scaler) (enlargement of figure 8 ) fig 10. luminance transfer characteristic in rgb (excluding scaler) 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) f (mhz) mgb708 - 30 - 18 - 42 - 6 6 0 g v (db) - 54 0 14 10 12 8 246 - 24 - 12 - 36 - 48
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 20 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.1 reset conditions to activate the reset, a pulse of at least 2 crystal clocks duration is required. during reset ( rese = low) plus an extra 32 crystal clock periods, fsvgc, vsvgc, cbo, hsvgc and ttx_sres are set to input mode and hsm_csync and vsm are set to 3-state. a reset also forces the i 2 c-bus interface to abort any running bus transfer and sets it into receive condition. after reset, the state of the i/os and other functions is de?ned by the strapping pins until an i 2 c-bus access rede?nes the corresponding registers; see t ab le 5 . fig 11. color difference transfer characteristic in rgb (excluding scaler) f (mhz) mgb706 - 30 - 18 - 42 - 6 6 0 g v (db) - 54 0 14 10 12 8 246 - 24 - 12 - 36 - 48 table 5. strapping pins pin tied preset fsvgc (pin g1) low ntsc m encoding, pixclk ?ts to 640 480 graphics input high pal b/g encoding, pixclk ?ts to 640 480 graphics input vsvgc (pin f1) low 4 : 2 : 2 y-c b -c r graphics input (format 0) high 4 : 4 : 4 rgb graphics input (format 3) cbo (pin g3) low input demultiplex phase: lsb = low high input demultiplex phase: lsb = high hsvgc (pin e3) low input demultiplex phase: msb = low high input demultiplex phase: msb = high ttxrq_xclko2 (pin c4) low slave (fsvgc, vsvgc and hsvgc are inputs, internal color bar is active) high master (fsvgc, vsvgc and hsvgc are outputs)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 21 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.2 input formatter the input formatter converts all accepted pd input data formats, either rgb or y-c b -c r , to a common internal rgb or y-c b -c r data stream. when double-edge clocking is used, the data is internally split into portions ppd1 and ppd2. the clock edge assignment must be set according to the i 2 c-bus control bits slot and edge for correct operation. if y-c b -c r is being applied as a 27 mb/s data stream, the output of the input formatter can be used directly to feed the video encoder block. the horizontal upscaling is supported via the input formatter. according to the programming of the pixel clock dividers (see section 8.10 ), it will sample up the data stream to 1 ,2 or 4 the input data rate. an optional interpolation ?lter is available. the clock domain transition is handled by a 4 entries wide fifo which gets initialized every ?eld or explicitly at request. a bypass for the fifo is available, especially for high input data rates. 8.3 rgb lut the three 256-byte rams of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for rgb signals. in the event that the indexed color data is applied, the rams are addressed in parallel. the luts can either be loaded by an i 2 c-bus write access or can be part of the pixel data input through the pd port. in the latter case, 256 bytes 3 bytes for the r, g and b lut are expected at the beginning of the input video line, two lines before the line that has been de?ned as ?rst active line, until the middle of the line immediately preceding the ?rst active line. the ?rst 3 bytes represent the ?rst rgb lut data, and so on. 8.4 cursor insertion a 32 dots 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an i 2 c-bus write access to speci?c registers or in the pixel data input through the pd port. in the latter case, the 256 bytes de?ning the cursor bit map (2 bits per pixel) are expected immediately following the last rgb lut data in the line preceding the ?rst active line. the cursor bit map is set up as follows: each pixel occupies 2 bits. the meaning of these bits depends on the cmode i 2 c-bus register as described in t ab le 8 . transparent means that the input pixels are passed through, the cursor colors can be programmed in separate registers. the bit map is stored with 4 pixels per byte, aligned to the least signi?cant bit. so the ?rst pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. the ?rst index is the column, followed by the row; index 0,0 is the upper left corner. table 6. layout of a byte in the cursor bit map d7 d6 d5 d4 d3 d2 d1 d0 pixel n + 3 pixel n + 2 pixel n + 1 pixel n d1 d0 d1 d0 d1 d0 d1 d0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 22 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec for each direction, there are 2 registers controlling the position of the cursor, one controls the position of the hot spot, the other register controls the insertion position. the hot spot is the tip of the pointer arrow. it can have any position in the bit map. the actual position registers describe the co-ordinates of the hot spot. again 0,0 is the upper left corner. while it is not possible to move the hot spot beyond the left respectively upper screen border, this is perfectly legal for the right respectively lower border. it should be noted that the cursor position is described relative to the input resolution. 8.5 rgb y-c b -c r matrix rgb input signals to be encoded to pal or ntsc are converted to the y-c b -c r color space in this block. the color difference signals are fed through low-pass ?lters and formatted to a itu-r bt.601 like 4:2:2 data stream for further processing. a gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235. the matrix and formatting blocks can be bypassed for y-c b -c r graphics input. when the auxiliary vga mode is selected, the output of the cursor insertion block is immediately directed to the triple dac. 8.6 horizontal scaler the high quality horizontal scaler operates on the 4:2:2 data stream. its control engines compensate the color phase offset automatically. the scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. each input pixel is a programmable fraction of the current output pixel (xinc/4096). a special case is xinc = 0, this sets the scaling factor to 1. table 7. cursor bit map byte d7 d6 d5 d4 d3 d2 d1 d0 0 row 0 column 3 row 0 column 2 row 0 column 1 row 0 column 0 1 row 0 column 7 row 0 column 6 row 0 column 5 row 0 column 4 2 row 0 column 11 row 0 column 10 row 0 column 9 row 0 column 8 ... ... ... ... ... 6 row 0 column 27 row 0 column 26 row 0 column 25 row 0 column 24 7 row 0 column 31 row 0 column 30 row 0 column 29 row 0 column 28 ... ... ... ... ... 254 row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24 255 row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28 table 8. cursor modes cursor pattern cursor mode cmode = 0 cmode = 1 00 second cursor color second cursor color 01 ?rst cursor color ?rst cursor color 10 transparent transparent 11 inverted input auxiliary cursor color
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 23 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec if the SAA7108AE; saa7109ae input data is in accordance with itu-r bt.656 , the scaler enters another mode. in this event, xinc needs to be set to 2048 for a scaling factor of 1. with higher values, upscaling will occur. the phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. small fifos rearrange a 4:2:2 data stream at the scaler output. 8.7 vertical scaler and anti-?icker ?lter the functions scaling, anti-flicker filter (aff) and re-interlacing are implemented in the vertical scaler. besides the entire input frame, it receives the ?rst and last lines of the border to allow anti-?icker ?ltering. the circuit generates the interlaced output ?elds by scaling down the input frames with different offsets for odd and even ?elds. increasing the yskip setting reduces the anti-?icker function. a yskip value of 4095 switches it off; see t ab le 107 . an additional, programmable vertical ?lter supports the anti-?icker function. this ?lter is not available at upscaling factors of more than 2. the programming is similar to the horizontal scaler. for the re-interlacing, the resolutions of the offset registers are not suf?cient, so the weighting factors for the ?rst lines can also be adjusted. yinc = 0 sets the scaling factor to 1; yiwgto and yiwgte must not be 0. due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. the maximum factor depends on the setting of the anti-?icker function and can be derived from the formulae given in section 8.20 . an additional upscaling mode allows to increase the upscaling factor to maximum 4 as it is required for the old vga modes like 320 240. 8.8 fifo the fifo acts as a buffer to translate from the pixclk clock domain to the xtal clock domain. the write clock is pixclk and the read clock is xtal. an under?ow or over?ow condition can be detected via the i 2 c-bus read access. in order to avoid under?ows and over?ows, it is essential that the frequency of the synthesized pixclk matches to the input graphics resolution and the desired scaling factor. 8.9 border generator when the graphics picture is to be displayed as interlaced pal, ntsc, s-video or rgb on a tv screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a tv set. the desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be ?lled in the border generator with an arbitrary true color tint.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 24 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.10 oscillator and discrete time oscillator (dto) the master clock generation is realized as a 27 mhz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd harmonic crystal. the crystal clock supplies the dto of the pixel clock synthesizer, the video encoder and the i 2 c-bus control block. it also usually supplies the triple dac, with the exception of the auxiliary vga mode, where the triple dac is clocked by the pixel clock (pixclk). the dto can be programmed to synthesize all relevant pixel clock frequencies between circa 40 mhz and 85 mhz. two programmable dividers provide the actual clock to be used externally and internally. the dividers can be programmed to factors of 1, 2, 4 and 8. for the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden. the internal clock can be switched completely to the pixel clock input. in this event, the input fifo is useless and will be bypassed. the entire pixel clock generation can be locked to the vertical frequency. both pixel clock dividers get re-initialized every ?eld. optionally, the dto can be cleared with each v-sync. at proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. this is required for some graphic controllers. 8.11 low-pass clock generation circuit (cgc) this block reduces the phase jitter of the synthesized pixel clock. it works as a tracking ?lter for all relevant synthesized pixel clock frequencies. 8.12 encoder 8.12.1 video path the encoder generates luminance and color subcarrier output signals from the y, c b and c r baseband signals, which are suitable for use as cvbs or separate y and c signals. input to the encoder, at 27 mhz clock (e.g. dvd), is either originated from computer graphics at pixel clock, fed through the fifo and border generator, or a itu-r bt.656 style signal. luminance is modi?ed in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). a blanking level can be set after insertion of a ?xed synchronization pulse tip level, in accordance with standard composite synchronization schemes. other manipulations used for the macrovision anti-taping process, such as additional insertion of agc super-white pulses (programmable in height), are supported by the SAA7108AE only. to enable easy analog post ?ltering, luminance is interpolated from a 13.5 mhz data rate to a 27 mhz data rate, thereby providing luminance in a 10-bit resolution. the transfer characteristics of the luminance interpolation ?lter are illustrated in figure 8 and figure 9 . appropriate transients at start/end of active video and for synchronization pulses are ensured.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 25 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec chrominance is modi?ed in gain (programmable separately for c b and c r ), and a standard dependent burst is inserted, before baseband color signals are interpolated from a 6.75 mhz data rate to a 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher color bandwidth, which can be used for the y and c output. the transfer characteristics of the chrominance interpolation ?lter are illustrated in figure 6 and figure 7 . the amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. after the succeeding quadrature modulator, color is provided on the subcarrier in 10-bit resolution. the numeric ratio between the y and c outputs is in accordance with the standards. 8.12.2 teletext insertion and encoding (not simultaneously with real-time control) pin ttx_sres receives a wst or nabts teletext bitstream sampled at the crystal clock. at each rising edge of the output signal (ttxrq) a single teletext bit has to be provided after a programmable delay at input pin ttx_sres. phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing suf?cient small phase jitter on the output text lines. ttxrq_xclko2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both ?elds. the internal insertion window for text is set to 360 (pal wst), 296 (ntsc wst) or 288 (nabts) teletext bits including clock run-in bits. the protocol and timing are illustrated in figure 66 . alternatively, this pin can be provided with a buffered crystal clock (xclk) of 13.5 mhz. 8.12.3 video programming system (vps) encoding five bytes of vps information can be loaded via the i 2 c-bus and will be encoded in the appropriate format into line 16. 8.12.4 closed caption encoder using this circuit, data in accordance with the speci?cation of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per ?eld), each pair preceded by run-in clocks and framing code, are possible. the actual line number in which data is to be encoded, can be modi?ed in a certain range. the data clock frequency is in accordance with the de?nition for ntsc m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz ?eld frequencies at 32 times the horizontal line frequency. 8.12.5 anti-taping (SAA7108AE only) for more information contact your nearest nxp semiconductors sales of?ce.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 26 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.13 rgb processor this block contains a dematrix in order to produce red, green and blue signals to be fed to a scart plug. before y, c b and c r signals are de-matrixed, individual gain adjustment for y and color difference signals and 2 times oversampling for luminance and 4 times oversampling for color difference signals is performed. the transfer curves of luminance and color difference components of rgb are illustrated in figure 10 and figure 11 . 8.14 triple dac both y and c signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. y and c signals are also combined into a 10-bit cvbs signal. the cvbs output signal occurs with the same processing delay as the y, c and optional rgb or c r -y-c b outputs. absolute amplitude at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of the conversion ranges. red, green and blue signals are also converted from digital-to-analog, each providing a 10-bit resolution. the reference currents of all three dacs can be adjusted individually in order to adapt for different output signals. in addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. alternatively, all currents can be switched off to reduce power dissipation. all three outputs can be used to sense for an external load (usually 75 w ) during a pre-de?ned output. a ?ag in the i 2 c-bus status byte re?ects whether a load is applied or not. in addition, an automatic sense mode can be activated which indicates a 75 w load at any of the three outputs at the dedicated interrupt pin tvd. if the SAA7108AE; saa7109ae is required to drive a second (auxiliary) vga monitor or an hdtv set, the dacs receive the signal coming from the hd data path. in this event, the dacs are clocked at the incoming pixclki instead of the 27 mhz crystal clock used in the video encoder. 8.15 hd data path this data path allows the SAA7108AE; saa7109ae to be used with vga or hdtv monitors. it receives its data directly from the cursor generator and supports rgb and y- p b -p r output formats (rgb not with y-p b -p r input formats). no scaling is done in this mode. a gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. this enables sync pulses to be added to the signal as it is required for display units expecting signals with sync pulses, either regular or 3-level syncs.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 27 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.16 timing generator the synchronization of the SAA7108AE; saa7109ae is able to operate in two modes; slave mode and master mode. in slave mode, the circuit accepts sync pulses on the bidirectional fsvgc (frame sync), vsvgc (vertical sync) and hsvgc (horizontal sync) pins: the polarities of the signals can be programmed. the frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. if the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the hfs and vfs bits. hsvgc and vsvgc are not necessary in this case, so it is possible to switch the pins to output mode. alternatively, the device can be triggered by auxiliary codes in a itu-r bt.656 data stream via pd7 to pd0. only vertical frequencies of 50 hz and 60 hz are allowed with the SAA7108AE; saa7109ae. in slave mode, it is not possible to lock the encoders color carrier to the line frequency with the phres bits. in the (more common) master mode, the time base of the circuit is continuously free-running. the ic can output a frame sync at pin fsvgc, a vertical sync at pin vsvgc, a horizontal sync at pin hsvgc and a composite blanking signal at pin cbo. all of these signals are de?ned in the pixclk domain. the duration of hsvgc and vsvgc are ?xed, they are 64 clocks for hsvgc and 1 line for vsvgc. the leading slopes are in phase and the polarities can be programmed. the input line length can be programmed. the ?eld length is always derived from the ?eld length of the encoder and the pixel clock frequency that is being used. cbo acts as a data request signal. the circuit accepts input data at a programmable number of clocks after cbo goes active. this signal is programmable and it is possible to adjust the following (see figure 64 and figure 65 ): ? the horizontal offset ? the length of the active part of the line ? the distance from active start to ?rst expected data ? the vertical offset separately for odd and even ?elds ? the number of lines per input ?eld in most cases, the vertical offsets for odd and even ?elds are equal. if they are not, then the even ?eld will start later. the SAA7108AE; saa7109ae will also request the ?rst input lines in the even ?eld, the total number of requested lines will increase by the difference of the offsets. as stated above, the circuit can be programmed to accept the look-up and cursor data in the ?rst 2 lines of each ?eld. the timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. the additional request pulses will be suppressed with lutl set to logic 0; see t ab le 132 . the other vertical timings do not change in this case, so the ?rst active line can be number 2, counted from 0.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 28 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.17 pattern generator for hd sync pulses the pattern generator provides appropriate synchronization patterns for the video data path in auxiliary monitor or hdtv mode. it provides maximum ?exibility in terms of raster generation for all interlaced and non-interlaced computer graphics or atsc formats. the sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values in the outgoing data stream at speci?ed times. it can also be used to generate digital signals associated with time events. these can be used as digital horizontal and vertical synchronization signals on pins hsm_csync and vsm. the picture position is adjustable through the programmable relationship between the sync pulses and the video contents. the generation of embedded analog sync pulses is bound to a number of events which can be de?ned for a line. several of these line timing de?nitions can exist in parallel. for the ?nal sync raster composition a certain sequence of lines with different sync event properties has to be de?ned. the sequence speci?es a series of line types and the number of occurrences of this speci?c line type. once the sequence has been completed, it restarts from the beginning. all pulse shapes are ?ltered internally in order to avoid ringing after analog post ?lters. the sequence of the generated pulse stream must ?t precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame. the sync engines ?exibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. figure 12 illustrates the context between the various tables. the ?rst table serves as an array to hold the correct sequence of lines that compose the synchronization raster; it can contain up to 16 entries. each entry holds a 4-bit index to the next table and a 10-bit counter value which speci?es how often this particular line is invoked. if the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. the 4-bit index in the line count array points to the line type array. it holds up to 15 entries (index 0 is not used), index 1 points to the ?rst entry, index 2 to the second entry of the line type array etc. each entry of the line type array can hold up to 8 index pointers to another table. these indices point to portions of a line pulse pattern: a line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line. each index of this table points to a particular line of the next table in the linked list. this table is called the line pattern array and each of the up to seven entries stores up to four pairs of a duration in pixel clock cycles and an index to a value table. the table entries are used to de?ne portions of a line representing a certain value for a certain number of clock cycles. the value speci?ed in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. if bit 4 (msb) of the index is logic 1, the value is inserted into the g or y signal only; if bi t 4 = 0, the associated value is inserted into all three signals. two additional bits of the entries in the value array (lsbs of the second byte) determine if the associated events appear as a digital pulse on the hsm_csync and/or vsm outputs.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 29 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec to ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster which is de?ned as width and height. a trigger position can be speci?ed as an x, y co-ordinate within the overall dimensions of the screen raster. if the x, y counter matches the speci?ed co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values. the listing in t ab le 9 outlines an example on how to set up the sync tables for a 1080i hd raster. important note: due to a problem in the programming interface, writing to the line pattern array (address d2) might destroy the data of the line type array (address d1). a work around is to write the line pattern array data before writing the line type array. reading of the arrays is possible but all address pointers must be initialized before the next write operation. fig 12. context between the pattern generator tables for dh sync pulses table 9. example for setup of the sync tables sequence (hexadecimal) comment write to subaddress d0h 00 points to ?rst entry of line count array (index 0) 05 20 generate 5 lines of line type index 2 (this is the second entry of the line type array); will be the ?rst vertical raster pulse 01 40 generate 1 line of line type index 4; will be sync-black-sync-black sequence after the ?rst vertical pulse 0e 60 generate 14 lines of line type index 6; will be the following lines with sync-black sequence mbl797 4-bit line type index 10-bit duration 4-bit value index 10-bit duration 4-bit value index 10-bit duration 4-bit value index 10-bit duration 4-bit value index 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 10-bit line count line count array 16 entries line type array 15 entries 8 + 2-bit value line pattern array 7 entries line count pointer event type pointer line pattern pointer pattern pointer line type pointer value array 8 entries
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 30 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 1c 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence 01 50 generate 1 line of line type index 5; will be the following line (line 563) with sync-black-sync-black-null sequence (null is equivalent to sync tip) 04 20 generate 4 lines of line type index 2; will be the second vertical raster pulse 01 30 generate 1 line of line type index 3; will be the following line with sync-null-sync-black sequence 0f 60 generate 15 lines of line type index 6; will be the following lines with sync-black sequence 1c 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence; now, 1125 lines are de?ned write to subaddress d2h (insertion is done into all three analog output signals) 00 points to ?rst entry of line pattern array (index 1) 6f 33 2b 30 00 00 00 00 880 value(3) + 44 value(3); (subtract 1 from real duration) 6f 43 2b 30 00 00 00 00 880 value(4) + 44 value(3) 3b 30 bf 03 bf 03 2b 30 60 value(3) + 960 value(0) + 960 value(0) + 44 value(3) 2b 10 2b 20 57 30 00 00 44 value(1) + 44 value(2) + 88 value(3) 3b 30 bf 33 bf 33 2b 30 60 value(3) + 960 value(3) + 960 value(3) + 44 value(3) write to subaddress d1h 00 points to ?rst entry of line type array (index 1) 34 00 00 00 use pattern entries 4 and 3 in this sequence (for sync and active video) 24 24 00 00 use pattern entries 4, 2, 4 and 2 in this sequence (for 2 sync-black-null-black) 24 14 00 00 use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) 14 14 00 00 use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black) 14 24 00 00 use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) 54 00 00 00 use pattern entries 4 and 5 in this sequence (for sync-black) write to subaddress d3h (no signals are directed to pins hsm_csync and vsm) 00 points to ?rst entry of value array (index 0) cc 00 black level, to be added during active video 80 00 sync level low (minimum output voltage) 0a 00 sync level high (3-level sync) cc 00 black level (needed elsewhere) table 9. example for setup of the sync tables continued sequence (hexadecimal) comment
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 31 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 8.18 i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbit/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write and read, except two read only status bytes. the register bit map consists of an rgb look-up table (lut), a cursor bit map and control registers. the lut contains three banks of 256 bytes, where each rgb triplet is assigned to one address. thus a write access needs the lut address and three data bytes following subaddress ffh. for further write access auto-incrementing of the lut address is performed. the cursor bit map access is similar to the lut access but contains only a single byte per address. the i 2 c-bus slave address is de?ned as 88h. 8.19 power-down modes in order to reduce the power consumption, the SAA7108AE; saa7109ae supports 2 power-down modes, accessible via the i 2 c-bus. the analog power-down mode (downa = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. the digital power-down mode (downd = 1) turns off all internal clocks and sets the digital outputs to low except the i 2 c-bus interface. the ic keeps its programming and can still be accessed in this mode, however not all registers can be read from or written to. reading or writing to the look-up tables, the cursor and the hd sync generator require a valid pixel clock. the typical supply current in full power-down is approximately 5 ma. because the analog power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. if there is no pixel clock, the ic is not able to set its outputs to low. so, in most cases, downa and downd should be set to logic 1 simultaneously. if the eidiv bit is logic 1, it should be set to logic 0 before power-down. 8.20 programming the graphics acquisition scaler of the video encoder the encoder section needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream of data from its data source. because there is no frame memory isolating the data streams, restrictions apply to the input frame timings. input and output processing of the encoder section are only coupled through the vertical frequencies. in master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing. in slave mode, the encoder receives them. the parameters of the input ?eld are mainly given by the memory capacity of the encoder section. the rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. therefore, the vertical active video times (and the vertical frequencies) need to be the same. 80 00 null (identical to sync level low) write to subaddress dch 0b insertion is active, gain for signal is adapted accordingly table 9. example for setup of the sync tables continued sequence (hexadecimal) comment
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 32 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the second rule is that there has to be data in the buffer fifo when the encoder enters the active video area. therefore, the vertical offset in the input path needs to be a bit shorter than the offset of the encoder. the following gives the set of equations required to program the ic for the most common application: a post processor in master mode with non-interlaced video input data. some variables are de?ned below: ? inpix: the number of active pixels per input line ? inppl: the length of the entire input line in pixel clocks ? inlin: the number of active lines per input ?eld/frame ? tpclk: the pixel clock period ? riepclk: the ratio of internal to external pixel clock ? outpix: the number of active pixels per output line ? outlin: the number of active lines per output ?eld ? txclk: the encoder clock period (37.037 ns) 8.20.1 tv display window at 60 hz, the ?rst visible pixel has the index 256, 710 pixels can be encoded; at 50 hz, the index is 284, 702 pixels can be visible. the output lines should be centred on the screen. it should be noted that the encoder has 2 clocks per pixel; see t ab le 76 . adwhs = 256 + 710 - outpix (60 hz); adwhs = 284 + 702 - outpix (50 hz); adwhe = adwhs + outpix 2 (all frequencies) for vertical, the procedure is the same. at 60 hz, the ?rst line with video information is number 19, 240 lines can be active. for 50 hz, the numbers are 23 and 287; see t ab le 84 . (60 hz); (50 hz); lal = fal + outlin (all frequencies) most tv sets use overscan, and not all pixels are visible. there is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. a reasonable underscan factor is 10 %, giving approximately 640 output pixels per line. 8.20.2 input frame and pixel clock the total number of pixel clocks per line and the input horizontal offset need to be chosen next. the only constraint is that the horizontal blanking has at least 10 clock pulses. the required pixel clock frequency can be determined in the following way: due to the limited internal fifo size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. the scaler also has to process the ?rst and last border lines for the anti-?icker function. thus: fal 19 240 outlin C 2 --------------------------------- + = fal 23 287 outlin C 2 --------------------------------- + =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 33 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec (60 hz) (50 hz) and for the pixel clock generator (all frequencies); see t ab le 88 and t ab le 89 . the divider pcle should be set according to t ab le 89 . pcli may be set to a lower or the same value. setting a lower value means that the internal pixel clock is higher and the data get sampled up. the difference may be 1 at 640 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. this allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter riepclk). (all frequencies) the equations ensure that the last line of the ?eld has the full number of clock cycles. many graphic controllers require this. note that the bit pclsy needs to be set to ensure that there is not even a fraction of a clock left at the end of the ?eld. 8.20.3 horizontal scaler xofs can be chosen arbitrarily, the condition being that xofs + xpix hlen is ful?lled. values given by the vesa display timings are preferred. hlen = inppl riepclk - 1 xinc needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. 8.20.4 vertical scaler the input vertical offset can be taken from the assumption that the scaler should just have ?nished writing the ?rst line when the encoder starts reading it: (60 hz) (50 hz) in most cases the vertical offsets will be the same for odd and even ?elds. the results should be rounded down. ypix = inlin yskip de?nes the anti-?icker function. 0 means maximum ?icker reduction but minimum vertical bandwidth, 4095 gives no ?icker reduction and maximum bandwidth. note that the maximum value for yinc is 4095. it might be necessary to reduce the value of yskip to ful?l this requirement. tpclk 262.5 1716 txclk inppl integer inlin 2 + outlin ----------------------- 262.5 ? ?? ----------------------------------------------------------------------------------------- - = tpclk 312.5 1728 txclk inppl integer inlin 2 + outlin ----------------------- 312.5 ? ?? ----------------------------------------------------------------------------------------- - = pcl txclk tpclk --------------- 2 20 pcle + = pcli pcle riepclk log 2 log ---------------------------- - C = xpix inpix 2 ------------- - riepclk = xinc outpix inpix ------------------ 4096 riepclk -------------------- = yofs fal 1716 txclk inppl tpclk --------------------------------------------------- 2.5 C = yofs fal 1728 txclk inppl tpclk --------------------------------------------------- 2.5 C =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 34 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec when yinc = 0 it sets the scaler to scaling factor 1. the initial weighting factors must not be set to 0 in this case. yiwgte may go negative. in this event, yinc should be added and yofse incremented. this can be repeated as often as necessary to make yiwgte positive. it should be noted that these equations assume that the input is non-interlaced but the output is interlaced. if the input is interlaced, the initial weighting factors need to be adapted to obtain the proper phase offsets in the output frame. if vertical upscaling beyond the upper capabilities is required, the parameter yupsc may be set to logic 1. this extends the maximum vertical scaling factor by a factor of 2. only the parameter yinc is affected, it needs to be divided by two to get the same effect. there are restrictions in this mode: ? the vertical ?lter yfil is not available in this mode; the circuit will ignore this value ? the horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. this is 710 internal pixel clocks or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is also limited to less than ~ 1.5. in this case a normal blanking length is suf?cient 8.21 input levels and formats the SAA7108AE; saa7109ae accepts digital y, c b ,c r or rgb data with levels (digital codes) in accordance with itu-r bt.601 . an optional gain adjustment also allows to accept data with the full level swing of 0 to 255. for c and cvbs outputs, deviating amplitudes of the color difference signals can be compensated for by independent gain control setting, while gain for luminance is set to prede?ned values, distinguishable for 7.5 ire set-up or without set-up. the rgb, respectively c r -y-c b path features an individual gain setting for luminance (gy) and color difference signals (gcd). reference levels are measured with a color bar, 100 % white, 100 % amplitude and 100 % saturation. the encoder section of the SAA7108AE; saa7109ae has special input cells for the vgc port. they operate at a wider supply voltage range and have a strict input threshold at 1 2 v dd(dvo) . to achieve full speed of these cells, the eidiv bit needs to be set to logic 1. note that the impedance of these cells is approximately 6 k w . this may cause trouble with the bootstrapping pins of some graphic chips. so the power-on reset forces the bit to logic 0, the input impedance is regular in this mode. yinc outlin inlin 2 + ----------------------- 1 yskip 4095 ---------------- - + ? ?? 4096 = yiwgto yinc 2 -------------- 2048 + = yiwgte yinc yskip C 2 ------------------------------------- =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 35 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] transformation: r = y + 1.3707 (c r - 128) g=y - 0.3365 (c b - 128) - 0.6982 (c r - 128) b = y + 1.7324 (c b - 128). table 10. itu-r bt.601 signal component levels color signals [1] y c b c r r g b white 235 128 128 235 235 235 yellow 210 16 146 235 235 16 cyan 170 166 16 16 235 235 green 145 54 34 16 235 16 magenta 106 202 222 235 16 235 red 81 90 240 235 16 16 blue 41 240 110 16 16 235 black 16 128 128 16 16 16 table 11. usage of bits slot and edge data slot control (example for format 0) slot edge 1st data 2nd data 0 0 at rising edge g3/y3 at falling edge r7/c r 7 0 1 at falling edge g3/y3 at rising edge r7/c r 7 1 0 at rising edge r7/c r 7 at falling edge g3/y3 1 1 at falling edge r7/c r 7 at rising edge g3/y3 table 12. pin assignment for input format 0 8 + 8 + 8-bit 4 :4:4 non-interlaced rgb/c b -y-c r pin falling clock edge rising clock edge pd11 g3/y3 r7/c r 7 pd10 g2/y2 r6/c r 6 pd9 g1/y1 r5/c r 5 pd8 g0/y0 r4/c r 4 pd7 b7/c b 7 r3/c r 3 pd6 b6/c b 6 r2/c r 2 pd5 b5/c b 5 r1/c r 1 pd4 b4/c b 4 r0/c r 0 pd3 b3/c b 3 g7/y7 pd2 b2/c b 2 g6/y6 pd1 b1/c b 1 g5/y5 pd0 b0/c b 0 g4/y4
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 36 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 13. pin assignment for input format 1 5 + 5 + 5-bit 4 :4:4 non-interlaced rgb pin falling clock edge rising clock edge pd7 g2 x pd6 g1 r4 pd5 g0 r3 pd4 b4 r2 pd3 b3 r1 pd2 b2 r0 pd1 b1 g4 pd0 b0 g3 table 14. pin assignment for input format 2 5 + 6 + 5-bit 4 :4:4 non-interlaced rgb pin falling clock edge rising clock edge pd7 g2 r4 pd6 g1 r3 pd5 g0 r2 pd4 b4 r1 pd3 b3 r0 pd2 b2 g5 pd1 b1 g4 pd0 b0 g3 table 15. pin assignment for input format 3 8 + 8 + 8-bit 4 :2:2 non-interlaced c b -y-c r pin falling clock edge n rising clock edge n falling clock edge n + 1 rising clock edge n + 1 pd7 c b 7(0) y7(0) c r 7(0) y7(1) pd6 c b 6(0) y6(0) c r 6(0) y6(1) pd5 c b 5(0) y5(0) c r 5(0) y5(1) pd4 c b 4(0) y4(0) c r 4(0) y4(1) pd3 c b 3(0) y3(0) c r 3(0) y3(1) pd2 c b 2(0) y2(0) c r 2(0) y2(1) pd1 c b 1(0) y1(0) c r 1(0) y1(1) pd0 c b 0(0) y0(0) c r 0(0) y0(1) table 16. pin assignment for input format 4 8 + 8 + 8-bit 4 :2:2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) pin rising clock edge n rising clock edge n + 1 rising clock edge n + 2 rising clock edge n + 3 pd7 c b 7(0) y7(0) c r 7(0) y7(1) pd6 c b 6(0) y6(0) c r 6(0) y6(1) pd5 c b 5(0) y5(0) c r 5(0) y5(1)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 37 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. pd4 c b 4(0) y4(0) c r 4(0) y4(1) pd3 c b 3(0) y3(0) c r 3(0) y3(1) pd2 c b 2(0) y2(0) c r 2(0) y2(1) pd1 c b 1(0) y1(0) c r 1(0) y1(1) pd0 c b 0(0) y0(0) c r 0(0) y0(1) table 17. pin assignment for input format 5 [1] 8-bit non-interlaced index color pin falling clock edge rising clock edge pd11 x x pd10 x x pd9 x x pd8 x x pd7 index7 x pd6 index6 x pd5 index5 x pd4 index4 x pd3 index3 x pd2 index2 x pd1 index1 x pd0 index0 x table 18. pin assignment for input format 6 8 + 8 + 8-bit 4 :4:4 non-interlaced rgb/c b -y-c r pin falling clock edge rising clock edge pd11 g4/y4 r7/c r 7 pd10 g3/y3 r6/c r 6 pd9 g2/y2 r5/c r 5 pd8 b7/c b 7 r4/c r 4 pd7 b6/c b 6 r3/c r 3 pd6 b5/c b 5 g7/y7 pd5 b4/c b 4 g6/y6 pd4 b3/c b 3 g5/y5 pd3 g0/y0 r2/c r 2 pd2 b2/c b 2 r1/c r 1 pd1 b1/c b 1 r0/c r 0 pd0 b0/c b 0 g1/y1 table 16. pin assignment for input format 4 continued 8 + 8 + 8-bit 4 :2:2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) pin rising clock edge n rising clock edge n + 1 rising clock edge n + 2 rising clock edge n + 3
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 38 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9. functional description of digital video decoder part 9.1 decoder 9.1.1 analog input processing the SAA7108AE; saa7109ae offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog ampli?er, anti-alias ?lter and video 9-bit cmos adc; see figure 16 . 9.1.2 analog control circuits the anti-alias ?lters are adapted to the line-locked clock frequency via a ?lter control circuit. the characteristic is shown in figure 13 . during the vertical blanking period gain and clamping control are frozen. 9.1.2.1 clamping the clamp control circuit controls the correct clamping of the analog input signals. the coupling capacitor is also used to store and ?lter the clamping voltage. an internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. the clamping levels for the two adc channels are ?xed for luminance (60) and chrominance (128). clamping time in normal use is set with the hcl pulse on the back porch of the video signal; see figure 14 and figure 15 . 9.1.2.2 gain control the gain control circuit receives (via the i 2 c-bus) the static gain levels for the two analog ampli?ers or controls one of these ampli?ers automatically via a built-in automatic gain control (agc) as part of the analog input control (aico). the agc for luminance is used to amplify a cvbs or y signal to the required signal amplitude, matched to the adcs input voltage range. the agc active time is the sync bottom of the video signal. fig 13. anti-alias ?lter f (mhz) 0 12 4 2 6 10 14 8 mgd138 - 18 - 30 - 6 6 0 - 12 - 24 - 36 v (db) - 42
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 39 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec signal (white) peak control limits the gain at signal overshoots. the in?uence of supply voltage variation within the speci?ed range is automatically eliminated by clamping and automatic gain control. the ?ow charts show more details of the agc; see figure 17 and figure 18 . fig 14. analog line with clamp (hcl) and gain range (hsy) fig 15. automatic gain range hcl mgl065 hsy analog line blanking tv line 1 60 255 gain clamp analog input level controlled adc input level maximum minimum range 9 db 0 db 0 db mhb325 + 3 db - 6 db (1 v (p-p) 18/56 w )
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 40 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 16. analog input processing using the SAA7108AE; saa7109ae as differential front-end with 9-bit adc holdg gafix wpoff gudl [ 1:0 ] gai [ 28:20 ] gai [ 18:10 ] hlnrs uptcv mode[3:0] hsy glimb glimt wipa sltca analog control vbsl source switch clamp circuit analog amplifier dac9 anti-alias filter bypass switch adc2 source switch clamp circuit analog amplifier dac9 anti-alias filter bypass switch adc1 cross-multiplexer vertical blanking control clamp control gain control anti-alias control mode control fuse [ 1:0 ] fuse [ 1:0 ] aosl [ 1:0 ] cvbs/chr cvbs/lum 99 ad1byp ad2byp m10 aout p11 p12 p13 p6 ai24 ai12 p9 ai22 ai1d p10 ai21 ai11 test selector and buffer 9 9 9 9 p8 ai2d p7 ai23 mhb892
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 41 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec x = system variable. y= ? agv - fgv ? > gudl. gudl = gain update level (adjustable). vblk = vertical blanking pulse. hsy = horizontal sync pulse. agv = actual gain value. fgv = frozen gain value. fig 17. gain ?ow chart analog input amplifier anti-alias filter adc luma/chroma decoder x hsy > 510 > 510 < 1 < 4 > 496 x = 0 x = 1 - 1/llc2 + 1/llc2 - 1/llc2 + / - 0 + 1/f + 1/l gain accumulator (18 bits) actual gain value 9-bit (agv) [ - 3/ + 6 db ] x stop hsy y update fgv mhb728 agv gain value 9-bit 1 0 1 0 10 1 0 1 0 1 0 10 1 0 0 1 1 0 1 0 vblk 1 0 no action 9 9 dac gain holdg
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 42 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec wipe = white peak level (254). sbot = sync bottom level (1). cll = clamp level [60 y (128 c)]. hsy = horizontal sync pulse. hcl = horizontal clamp pulse. fig 18. clamp and gain ?ow 10 + clamp - clamp no clamp 10 10 01 10 mgc647 fast - gain slow + gain + gain - gain hcl hsy adc < sbot > wipe < cll analog input gain -> <- clamp vblk no blanking active 10
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 43 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.1.3 chrominance and luminance processing fig 19. chrominance and luminance processing mhb532 cvbs-in or chr-in code brig[7:0] cont[7:0] satn[7:0] huec[7:0] dcvf quadrature demodulator pal delay line secam recombination phase demodulator amplitude detector burst gate accumulator loop filter low-pass 1 downsampling subcarrier generation 2 fctc acgc cgain [ 6:0 ] idel [ 3:0 ] rtco c b - c r adjustment secam processing f h /2 switch signal adaptive comb filter ccomb ycomb ldel byps lufi [ 3:0 ] cstd [ 2:0 ] ydel [ 2:0 ] low-pass 2 chbw chroma gain control interpolation low-pass 3 lubw quadrature modulator cdto cstd [ 2:0 ] subcarrier generation 1 chrominance increment dto reset subcarrier increment generation and divider chrominance increment delay ldel ycomb c b -c r subtractor delay compensation cvbs-in or y-in chr luminance-peaking or low-pass, y-delay adjustment lcbw [ 2:0 ] y y/cvbs dbri [ 7:0 ] dcon [ 7:0 ] dsat [ 7:0 ] rawg [ 7:0 ] rawo [ 7:0 ] colo brightness contrast saturation control raw data gain and offset control ldel ycomb y-out/ cvbs-out c b - c r -out href-out set_raw set_vbi set_raw set_vbi set_raw set_vbi set_raw set_vbi c b - c r c b - c r c b - c r
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 44 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.1.3.1 chrominance path the 9-bit cvbs or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). the frequency is dependent on the chosen color standard. the time-multiplexed output signals of the multipliers are low-pass ?ltered (low-pass 1). eight characteristics are programmable via lcbw2 to lcbw0 to achieve the desired bandwidth for the color difference signals (pal, ntsc) or the 0 and 90 fm signals (secam). the chrominance low-pass 1 characteristic also in?uences the grade of cross luminance reduction during horizontal color transients (large chrominance bandwidth means strong suppression of cross luminance). if the y-comb ?lter is disabled by ycomb = 0 the ?lter in?uences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth). the low-pass ?ltered signals are fed to the adaptive comb ?lter block. the chrominance components are separated from the luminance via a two-line vertical stage (four lines for pal standards) and a decision logic between the ?ltered and the non-?ltered output signals. this block is bypassed for secam signals. the comb ?lter logic can be enabled independently for the succeeding luminance and chrominance processing by ycomb (subaddress 09h, bit 6) and/or ccomb (subaddress 0eh, bit 0). it is always bypassed during vbi or raw data lines programmable by the lcrn registers (subaddresses 41h to 57h); see section 9.2 . the separated c b -c r components are further processed by a second ?lter stage (low-pass 2) to modify the chrominance bandwidth without in?uencing the luminance path. its characteristic is controlled by chbw (subaddress 10h, bit 3). for the complete transfer characteristic of low-pass ?lters 1 and 2, see figure 20 and figure 21 . the secam processing (bypassed for qam standards) contains the following blocks: ? baseband bell ?lters to reconstruct the amplitude and phase equalized 0 and 90 fm signals ? phase demodulator and differentiator (fm-demodulation) ? de-emphasis ?lter to compensate the pre-emphasized input signal, including frequency offset compensation (db or dr white carrier values are subtracted from the signal, controlled by the secam switch signal) the succeeding chrominance gain control block ampli?es or attenuates the c b -c r signal according to the required itu 601/656 levels. it is controlled by the output signal from the amplitude detection circuit within the burst processing block. the burst processing block provides the feedback loop of the chrominance pll and contains the following: ? burst gate accumulator ? color identi?cation and color killer ? comparison nominal/actual burst amplitude (pal/ntsc standards only) ? loop ?lter chrominance gain control (pal/ntsc standards only)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 45 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec ? loop ?lter chrominance pll (only active for pal/ntsc standards) ? pal/secam sequence detection, h/2-switch generation the increment generation circuit produces the discrete time oscillator (dto) increment for both subcarrier generation blocks. it contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). the pal delay line block eliminates crosstalk between the chrominance channels in accordance with the pal standard requirements. for ntsc color standards the delay line can be used as an additional vertical ?lter. if desired, it can be switched off by dcvf = 1. it is always disabled during vbi or raw data lines programmable by the lcrn registers (subaddresses 41h to 57h); see section 9.2 . the embedded line delay is also used for secam recombination (cross-over switches).
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 46 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 20. transfer characteristics of the chrominance low-pass at chbw = 0 mhb533 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (mhz) (1) (2) (3) (4) (5) (6) (7) (8) (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 47 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 21. transfer characteristics of the chrominance low-pass at chbw = 1 mhb534 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (mhz) (1) (2) (3) (4) (5) (6) (7) (8) (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 48 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.1.3.2 luminance path the rejection of the chrominance components within the 9-bit cvbs or y input signal is achieved by subtracting the remodulated chrominance signal from the cvbs input. the comb ?ltered c b -c r components are interpolated (upsampled) by the low-pass 3 block. its characteristic is controlled by lubw (subaddress 09h, bit 4) to modify the width of the chrominance notch without in?uencing the chrominance path. the programmable frequency characteristics available, in conjunction with the lcbw2 to lcbw0 settings, can be seen in figure 22 to figure 25 . it should be noted that these frequency curves are only valid for y-comb disabled ?lter mode (ycomb = 0). in comb ?lter mode the frequency response is ?at. the center frequency of the notch is automatically adapted to the chosen color standard. the interpolated c b -c r samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. this second dto is locked to the ?rst subcarrier generator by an increment delay circuit matched to the processing delay, which is different for pal and ntsc standards according to the chosen comb ?lter algorithm. the two modulated signals are ?nally added to build the remodulated chrominance signal. the frequency characteristic of the separated luminance signal can be further modi?ed by the succeeding luminance ?lter block. it can be con?gured as peaking (resolution enhancement) or low-pass block by lufi3 to lufi0 (subaddress 09h, bits 3 to 0). the 16 resulting frequency characteristics can be seen in figure 26 . the lufi3 to lufi0 settings can be used as a user programmable sharpness control. the luminance ?lter block also contains the adjustable y-delay part; programmable by ydel2 to ydel0 (subaddress 11h, bits 2 to 0).
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 49 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 22. transfer characteristics of the luminance notch ?lter in 3.58 mhz mode (y-comb ?lter disabled) at lubw = 0 mhb535 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 50 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 23. transfer characteristics of the luminance notch ?lter in 3.58 mhz mode (y-comb ?lter disabled) at lubw = 1 mhb536 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 51 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 24. transfer characteristics of the luminance notch ?lter in 4.43 mhz mode (y-comb ?lter disabled) at lubw = 0 mhb537 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 52 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 25. transfer characteristics of the luminance notch ?lter in 4.43 mhz mode (y-comb ?lter disabled) at lubw = 1 mhb538 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 53 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 26. transfer characteristics of the luminance peaking/low-pass ?lter (sharpness) mhb539 - 1 0 1 2 3 4 5 6 7 8 9 v (db) v (db) f (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 (8) (7) (6) (5) (4) (3) (2) (1) (9) (10) (11) (12) (13) (14) (15) (16) - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 (1) lufi[3:0] = 0001. (2) lufi[3:0] = 0010. (3) lufi[3:0] = 0011. (4) lufi[3:0] = 0100. (5) lufi[3:0] = 0101. (6) lufi[3:0] = 0110. (7) lufi[3:0] = 0111. (8) lufi[3:0] = 0000. (9) lufi[3:0] = 1000. (10) lufi[3:0] = 1001. (11) lufi[3:0] = 1010. (12) lufi[3:0] = 1011. (13) lufi[3:0] = 1100. (14) lufi[3:0] = 1101. (15) lufi[3:0] = 1110. (16) lufi[3:0] = 1111.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 54 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.1.3.3 brightness contrast saturation (bcs) control and decoder output levels the resulting y (cvbs) and c b -c r signals are fed to the bcs block, which contains the following functions: ? chrominance saturation control by dsat7 to dsat0 ? luminance contrast and brightness control by dcon7 to dcon0 and dbri7 to dbri0 ? raw data (cvbs) gain and offset adjustment by rawg7 to rawg0 and rawo7torawo0 ? limiting y-c b -c r or cvbs to the values 1 (minimum) and 254 (maximum) to ful?l itu recommendation 601/656 itu recommendation 601/656 digital levels with default bcs (decoder) settings dcon[7:0] = 44h, dbri[7:0] = 80h and dsat[7:0] = 40h. equations for modi?cation to the y-c b -c r levels via bcs control i 2 c-bus bytes dbri, dcon and dsat. luminance: chrominance: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu recommendation 601/656 a. y output range. b. c b output range. c. c r output range. fig 27. y-c b -c r range for scaler input and x port output 001aac241 + 128 luminance 100 % + 16 0 + 235 black white + 255 001aac480 + 255 + 212 + 128 0 c b -component + 44 + 240 + 16 blue 100 % blue 75 % yellow 75 % yellow 100 % colorless 001aac481 + 255 + 212 + 128 0 c r -component + 44 + 240 + 16 red 100 % red 75 % cyan 75 % cyan 100 % colorless y out int dcon 68 ----------------- - y 128 C () dbri + = c r c b () out int dsat 64 --------------- c r c b 128 C (, ) 128 + =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 55 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.1.4 synchronization the pre?ltered luminance signal is fed to the synchronization stage. its bandwidth is further reduced to 1 mhz by a low-pass ?lter. the sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. the resulting output signal is applied to the loop ?lter to accumulate all phase deviations. internal signals (e.g. hcl and hsy) are generated in accordance with analog front-end requirements. the loop ?lter signal drives an oscillator to generate the line frequency control signal lfco; see figure 29 . the detection of pseudo syncs as part of the macrovision copy protection standard is also achieved within the synchronization circuit. the result is reported as ?ag copro within the decoder status byte at subaddress 1fh. 9.1.5 clock generation circuit the internal cgc generates all clock signals required for the video input processor. the internal signal lfco is a digital-to-analog converted signal provided by the horizontal pll. it is the multiple of the line frequency: ? 6.75 mhz = 429 f h (50 hz), or ? 6.75 mhz = 432 f h (60 hz) the lfco signal is multiplied by a factor of 2 and 4 in the internal pll circuit (including phase detector, loop ?ltering, vco and frequency divider) to obtain the output clock signals. the rectangular output clocks have a 50 % duty factor. cvbs levels with default settings rawg[7:0] = 64 and rawo[7:0] = 128. equation for modi?cation of the raw data levels via bytes rawg and rawo: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu recommendation 601/656. a. sources containing 7.5 ire black level offset (e.g. ntsc m). b. sources not containing black level offset. fig 28. cvbs (raw data) range for scaler input, data slicer and x port output luminance + 255 + 209 + 71 + 60 1 white sync bottom black shoulder black sync 001aac244 luminance + 255 + 199 + 60 1 white sync bottom black shoulder = black sync 001aac245 cvbs out int rawg 64 ----------------- cvbs nom 128 C () rawo + =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 56 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.1.6 power-on reset and ce input a missing clock, insuf?cient digital or analog v ddad supply voltages (below 2.7 v) will start the reset sequence; all outputs are forced to 3-state (see figure 30 ). the indicator output resd is low for approximately 128 llc after the internal reset and can be applied to reset other circuits of the digital tv system. it is possible to force a reset by pulling the ce input to ground. after the rising edge of ce and suf?cient power supply voltage, the outputs llc, llc2 and sdad return from 3-state to active, while the other signals have to be activated via programming. table 19. decoder clock frequencies clock frequency (mhz) xtalo 24.576 or 32.110 llc 27 llc2 13.5 llc4 (internal) 6.75 llc8 (virtual) 3.375 fig 29. block diagram of the clock generation circuit band pass fc = llc/4 zero cross detection phase detection loop filter divider 1/2 divider 1/2 oscillator mhb330 llc2 llc lfco
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 57 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec poc = power-on control. ce = chip enable input. xtalo = crystal oscillator output. llcint = internal system clock. resint = internal reset. llc = line-locked clock output. res = reset output. fig 30. power-on control circuit 001aad709 128 llc 896 llc digital delay some ms 20 m s to 200 m s pll delay < 1 ms res (internal reset) llc resint llcint xtalo ce poc v dda poc logic analog poc v ddd digital poc delay clock pll ce llc clk0 resint res
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 58 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.2 decoder output formatter the output interface block of the decoder part contains the itu 656 formatter for the expansion port data output xpd7 to xpd0 (for a detailed description see section 10.4.1 ) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. it also controls the selection of the reference signals for the rt port (rtco, rts0 and rts1) and the expansion port (xrh, xrv and xdq). the generation of the decoder data type control signals set_raw and set_vbi is also done within this block. these signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers lcr2 to lcr24 (see also section 11.2.4.2 subaddresses 41h to 57h ). for each lcr value from 2 to 23 the data type can be programmed individually; lcr2 to lcr23 refer to line numbers. the selection in lcr24 values is valid for the rest of the corresponding ?eld. the upper nibble contains the value for ?eld 1 (odd), the lower nibble for ?eld 2 (even). the relationship between lcr values and line numbers can be adjusted via voff8 to voff0, located in subaddresses 5bh (bit 4) and 5ah (bits 7 to 0) and foff subaddress 5bh (bit 7). the recommended values are voff[8:0] = 03h for 50 hz sources (with foff = 0) and voff[8:0] = 06h for 60 hz sources (with foff = 1), to accommodate line number conventions as used for pal, secam and ntsc standards; see figure 31 and figure 32 . table 20. data formats at decoder output data type number data type decoder output data format 0 teletext eurowst, ccst raw 1 european closed caption raw 2 video programming service (vps) raw 3 wide screen signalling bits raw 4 us teletext (wst) raw 5 us closed caption (line 21) raw 6 video component signal, vbi region y-c b -c r 4:2:2 7 cvbs data raw 8 teletext raw 9 vitc/ebu time codes (europe) raw 10 vitc/smpte time codes (usa) raw 11 reserved raw 12 us nabts raw 13 moji (japanese) raw 14 japanese format switch (l20/22) raw 15 video component signal, active video region y-c b -c r 4:2:2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 59 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec vertical line offset, voff[8:0] = 06h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59 h[7:0]); foff = 1 (subaddress 5bh[7]) fig 31. relationship of lcr to line numbers in 525 lines/60 hz systems 521 522 active video active video equalization pulses equalization pulses equalization pulses equalization pulses serration pulses serration pulses 523524525123456789 259 260 261 24 234 5678 9 262 263 264 265 266 267 268 269 270 271 272 line number (1st field) line number (2nd field) lcr 001aad425 10 11 nominal vbi lines f1 nominal vbi lines f2 active video active video 12 13 14 15 16 17 18 19 20 21 22 23 24 25 line number (1st field) line number (2nd field) lcr 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vertical line offset, voff[8:0] = 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59 h[7:0]); foff = 0 (subaddress 5bh[7]) fig 32. relationship of lcr to line numbers in 625 lines/50 hz systems 621 622 active video active video equalization pulses equalization pulses equalization pulses equalization pulses serration pulses serration pulses 623 624 625 1 2 3 4 5 line number (1st field) line number (2nd field) lcr 309 310 311 312 313 314 315 316 317 318 2 24 345 001aad426 67 nominal vbi lines f1 nominal vbi lines f2 active video active video 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 line number (1st field) line number (2nd field) lcr 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 60 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec (1) the inactive going edge of the v123 signal indicates whether the ?eld is odd or even. if href is active during the falling edge of v123, the ?eld is odd (?eld 1). if href is inactive during the falling edge of v123, the ?eld is even. the speci?c position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. the control signals listed above are available on pins rts0, rts1, xrh and xrv according to t ab le 21 . for further information see t ab le 160 , t ab le 161 and t ab le 162 . fig 33. vertical timing diagram for 50 hz/625 line systems mhb540 vgate vsto [ 8:0 ] = 134h vsta [ 8:0 ] = 15h (a) 1st field cvbs itu counting single field counting 1 1 2 2 3 3 4 4 5 5 6 6 7 7 ... ... 22 22 625 312 624 311 623 310 622 309 23 23 fid href f_itu656 v123 (1) vgate cvbs itu counting single field counting fid href f_itu656 v123 (1) vsto [ 8:0 ] = 134h vsta [ 8:0 ] = 15h (b) 2nd field 313 313 314 1 315 2 316 3 317 4 318 5 319 6 ... ... 335 22 312 312 311 311 310 310 309 309 336 23 table 21. control signals name rts0 (pin k13) rts1 (pin l10) xrh (pin n2) xrv (pin l5) href xxx- f_itu656 ---x v123 x x - x vgatexx- - fid x x - -
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 61 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec (1) the inactive going edge of the v123 signal indicates whether the ?eld is odd or even. if href is active during the falling edge of v123, the ?eld is odd (?eld 1). if href is inactive during the falling edge of v123, the ?eld is even. the speci?c position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. the control signals listed above are available on pins rts0, rts1, xrh and xrv according to t ab le 21 . for further information see t ab le 160 , t ab le 161 and t ab le 162 . fig 34. vertical timing diagram for 60 hz/525 line systems mhb541 vgate vsto [ 8:0 ] = 101h vsta [ 8:0 ] = 011h (a) 1st field cvbs itu counting single field counting 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ... ... 21 21 3 3 2 2 1 1 525 262 22 22 fid href f_itu656 v123 (1) vgate cvbs itu counting single field counting fid href f_itu656 v123 (1) vsto [ 8:0 ] = 101h vsta [ 8:0 ] = 011h (b) 2nd field 266 3 267 4 268 5 269 6 270 7 271 8 272 9 ... ... 284 21 265 2 264 1 263 263 262 262 285 22
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 62 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the signals href, hs, cref2 and cref are available on pins rts0 and/or rts1 (see t ab le 160 and t ab le 161 ); their polarity can be inverted via rtp0 and/or rtp1. the signals href and hs are available on pin xrh (see t ab le 162 ). fig 35. horizontal timing diagram (50/60 hz) 108 - 107 107 - 106 mhb542 cvbs input 140 1/llc 5 2/llc expansion port data output 12 2/llc 720 2/llc 144 2/llc 138 2/llc 720 2/llc burst processing delay adc to expansion port: 0 0 2 2/llc 2 2/llc href (60 hz) hs (60 hz) sync clipped 16 2/llc 1 2/llc programming range (step size: 8/llc) programming range (step size: 8/llc) hs (50 hz) href (50 hz) cref cref2 50 hz cref cref2 60 hz
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 63 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.3 scaler the high performance video scaler (hps) is based on the system as implemented in previous products (e.g. saa7140), but with some aspects enhanced. vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more ?exible video stream timing at the image port, discontinuous transfers and handshake. the internal data ?ow from block to block is discontinuous dynamically, due to the scaling process. the ?ow is controlled by internal data valid and data request ?ags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. depending on the actual programmed scaling parameters the effective buffer can exceed to an entire line. the access/bandwidth requirements to the vga frame buffer are reduced signi?cantly. the high performance video scaler in the SAA7108AE; saa7109ae has the following major blocks: ? acquisition control (horizontal and vertical timer) and task handling (the region/?eld/frame based processing) ? prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting ?lters, especially anti-aliasing for cif format ? brightness, saturation and contrast control for scaled output data ? line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, y-c b -c r 4:2:2) ? vertical scaling, with phase accurate linear phase interpolation (lpi) for zoom and downscale, or phase accurate accumulation mode (acm) for large downscaling ratios and better anti-alias suppression ? variable phase delay (vpd), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling ? output formatter for scaled y-c b -c r 4:2:2,y-c b -c r 4:1:1andy only (format also used for raw data) ? fifo, 32-bit wide, with 64 pixel capacity in y-c b -c r formats ? output interface, 8-bit or 16-bit (only if extended by h port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream the overall h and v zooming (hv_zoom) is restricted by the input/output data rate relationships. with a safety margin of 2 % for running in and running out, the maximum hv_zoom is equal to: for example: 1. input from decoder: 50 hz, 720 pixel, 288 lines, 16-bit data at 13.5 mhz data rate, 1 cycle per pixel; output: 8-bit data at 27 mhz, 2 cycles per pixel; the maximum hv_zoom is equal to: 0.98 t _ input _ field t _ v _ blanking C in _ pixel in _ lines out _ cycle _ per _ pix t _ out _ clk ------------------------------------------------------------------------------------------------------------------------------- ------------- - 0.98 20 ms 24 C 64 m s 720 288 2 37 ns ----------------------------------------------------- 1.18 =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 64 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 2. input from x port: 60 hz, 720 pixel, 240 lines, 8-bit data at 27 mhz data rate (itu 656), 2 cycles per pixel; output via i + h port: 16-bit data at 27 mhz clock, 1 cycle per pixel; the maximum hv_zoom is equal to: the video scaler receives its input signal from the video decoder or from the expansion port (x port). it gets 16-bit y-c b -c r 4 : 2 : 2 input data at a continuous rate of 13.5 mhz from the decoder. a discontinuous data stream can be accepted from the expansion port (x port), normally 8-bit wide itu 656 such as y-c b -c r data, accompanied by a pixel quali?er on xdq. the input data stream is sorted into two data paths, one for luminance (or raw samples) and one for time-multiplexed chrominance c b and c r samples. a y-c b -c r 4:1:1 input format is converted to 4:2:2 for the horizontal prescaling and vertical ?lter scaling operation. the scaler operation is de?ned by two programming pages a and b, representing two different tasks, that can be applied ?eld alternating or to de?ne two regions in a ?eld (e.g. with different scaling range, factors and signal source during odd and even ?elds). each programming page contains control for: ? signal source selection and formats ? task handling and trigger conditions ? input and output acquisition window de?nition ? h-prescaler, v-scaler and h-phase scaling raw vbi data is handled as a speci?c input format and needs its own programming page (equals own task). in vbi pass through operation the processing of prescaler and vertical scaling has to be disabled, however, the horizontal ?ne scaling vpd can be activated. upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms. these raw samples are transported through the image port as valid data and can be output as y only format. the lines are framed by sav and eav codes. 9.3.1 acquisition control and task handling (subaddresses 80h, 90h, 91h, 94h to 9fh and c4h to cfh) the acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the x port. the acquisition window is generated via pixel and line counters at the appropriate places in the data path. from x port only quali?ed pixels and lines (lines with quali?ed pixel) are counted. the acquisition window parameters are as follows: ? signal source selection regarding input video stream and formats from the decoder, or from the x port (programming bits scsrc[1:0] 91h[5:4] and fsc[2:0] 91h[2:0]) remark : the input of raw vbi data from the internal decoder should be controlled via the decoder output formatter and the lcr registers; see section 9.2 0.98 16.666 ms 22 C 64 m s 720 240 1 37 ns --------------------------------------------------------- - 2.34 =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 65 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec ? vertical offset de?ned in lines of the video source, parameter yo[11:0] 99h[3:0] 98h[7:0] ? vertical length de?ned in lines of the video source, parameter ys[11:0] 9bh[3:0] 9ah[7:0] ? vertical length de?ned in number of target lines, as a result of vertical scaling, parameter yd[11:0] 9fh[3:0] 9eh[7:0] ? horizontal offset de?ned in number of pixels of the video source, parameter xo[11:0] 95h[3:0] 94h[7:0] ? horizontal length de?ned in number of pixels of the video source, parameter xs[11:0] 97h[3:0] 96h[7:0] ? horizontal destination size de?ned in target pixels after ?ne scaling, parameter xd[11:0] 9dh[3:0] 9ch[7:0] the source start offset (xo11 to xo0 and yo11to yo0) opens the acquisition window, and the target size (xd11 to xd0 and yd11 to yd0) closes the window, however the window is cut vertically if there are less output lines than expected. the trigger events for the pixel and line counts are the horizontal and vertical reference edges as de?ned in subaddress 92h. the task handling is controlled by subaddress 90h; see section 9.3.1.2 . 9.3.1.1 input ?eld processing the trigger event for the ?eld sequence detection from external signals (x port) are de?ned in subaddress 92h. from the x port the state of the scalers horizontal reference signal at the time of the vertical reference edge is taken as ?eld sequence identi?er fid. for example, if the falling edge of the xrv input signal is the reference and the state of xrh input is logic 0 at that time, the detected ?eld id is logic 0. the bits xfdv[92h[7]] and xfdh[92h[6]] de?ne the detection event and state of the ?ag from the x port. for the default setting of xfdv and xfdh at 00 the state of the horizontal input at the falling edge of the vertical input is taken. the scaler directly gets a corresponding ?eld id information from the SAA7108AE; saa7109ae decoder path. the fid ?ag is used to determine whether the ?rst or second ?eld of a frame is going to be processed within the scaler and it is also used as trigger condition for the task handling (see bits strc[1:0] 90h[1:0]). according to itu 656, when fid is at logic 0 means ?rst ?eld of a frame. to ease the application, the polarities of the detection results on the x port signals and the internal decoder id can be changed via xfdh. as the v-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st ?elds from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd ?eld. this can be compensated for by switching the vertical trigger event, as de?ned by xdv0, to the opposite v-sync edge or by using the vertical scalers phase offsets. the vertical timing of the decoder can be seen in figure 33 and figure 34 . as the horizontal and vertical reference events inside the itu 656 data stream (from x port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 66 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.3.1.2 task handling the task handler controls the switching between the two programming register sets. it is controlled by subaddresses 90h and c0h. a task is enabled via the global control bits tea[80h[4]] and teb[80h[5]]. the handler is then triggered by events which can be de?ned for each register set. in the event of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit swrst[88h[5]] to logic 0. especially if the programming registers, related acquisition window and scaler are reprogrammed while a task is active, a software reset must be performed after programming. contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when swrst is at logic 0 it sets the internal state machines directly to their idle states. the start condition for the handler is de?ned by bits strc[1:0] 90h[1:0] and means: start immediately, wait for next v-sync, next fid at logic 0 or next fid at logic 1. the fid is evaluated, if the vertical and horizontal offsets are reached. when rptsk[90h[2]] is at logic 1 the actual running task is repeated (under the de?ned trigger conditions), before handing control over to the alternate task. to support ?eld rate reduction, the handler is also enabled to skip ?elds (bits fskp[2:0] 90h[5:3]) before executing the task. a toggle ?ag is generated (used for the correct output ?eld processing), which changes state at the beginning of a task, every time a task is activated; examples are given in section 9.3.1.3 . remarks : ? to activate a task the start condition must be ful?lled and the acquisition window offsets must be reached . for example, in case of start immediately, and two regions are de?ned for one ?eld, the offset of the lower region must be greater than (offset + length) of the upper region, if not, the actual counted h and v position at the end of the upper task is beyond the programmed offsets and the processing will wait for next v. table 22. processing trigger and start xdv1 92h[5] xdv0 92h[4] xdh 92h[2] description internal decoder : the processing triggers at the falling edge of the v123 pulse [see figure 33 (50 hz) and figure 34 (60 hz)], and starts earliest with the rising edge of the decoder href at line number: 0 1 0 4/7 (50/60 hz, 1st ?eld), respectively 3/6 (50/60 hz, 2nd ?eld) (decoder count) 0 0 0 2/5 (50/60 hz, 1st ?eld), respectively 2/5 (50/60 hz, 2nd ?eld) (decoder count) 000 external itu 656 stream : the processing starts earliest with sav at line number 23 (50 hz system), respectively line 20 (60 hz system) (according to itu 656 count)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 67 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec ? basically the trigger conditions are checked, when a task is activated . it is important to realize, that they are not checked while a task is inactive. so you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task a strc[1:0] = 2, yo[11:0] = 310 and task b strc[1:0] = 3, yo[11:0] = 310 results in an output ?eld rate of 50 3 hz). ? after power-on or software reset (via swrst[88h[5]]) task b gets priority over task a 9.3.1.3 output ?eld processing as a reference for the output ?eld processing, two signals are available for the back-end hardware. these signals are the input ?eld id from the scaler source and a toggle ?ag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. using a single or both tasks and reducing the ?eld or frame rate with the task handling function, the toggle information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. the toggle ?ag is not synchronized to the input ?eld detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly; see section 9.3.3 . when ofidc = 0, the scalers input ?eld id is available as output ?eld id on bit 6 of sav and eav, respectively on pin igp0 (igp1), if the fid output is selected. when ofidc[90h[6]] = 1, the toggle information is available as output ?eld id on bit 6 of sav and eav, respectively on pin igp0 (igp1), if the fid output is selected. additionally the bit 7 of sav and eav can be de?ned via conlh[90h[7]]. conlh[90h[7]] = 0 (default) sets bit 7 to logic 1, a logic 1 inverts the sav/eav bit 7. so it is possible to mark the output of both tasks by different sav/eav codes. this bit can also be seen as task ?ag on pins igp0 (igp1), if task output is selected.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 68 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] single task every ?eld; ofidc = 0; subaddress 90h at 40h; teb[80h[5]] = 0. [2] tasks are used to scale to different output windows, priority on task b after swrst. [3] both tasks at 1 2 frame rate; ofidc = 0; subaddresses 90h at 43h and c0h at 42h. [4] in examples 3 and 4 the association between input fid and tasks can be ?ipped, dependent on which time the swrst is de-asserte d. [5] task b at 2 3 frame rate constructed from neighboring motion phases; task a at 1 3 frame rate of equidistant motion phases; ofidc = 1; subaddresses 90h at 41h and c0h at 45h. [6] task a and b at 1 3 frame rate of equidistant motion phases; ofidc = 1; subaddresses 90h at 41h and c0h at 49h. [7] state of prior ?eld. [8] it is assumed that input/output fid = 0 (= upper lines); up = upper lines; lo = lower lines. [9] o = data output; no = no output. 9.3.2 horizontal scaling the overall horizontal required scaling factor has to be split into a binary and a rational value according to the following equation: where the parameter of the prescaler xpsc[5:0] = 1 to 63 and the parameter of vpd phase interpolation xscy[12:0] = 300 to 8191 (0 to 299 are only theoretical values). for example, 1 3.5 is to split in 1 4 1.14286. the binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay vpd circuitry, called horizontal ?ne scaling. the latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling schemes. prescaler and ?ne scaler create the horizontal scaler of the SAA7108AE; saa7109ae. using the accumulation length function of the prescaler (xacl[5:0] a1h[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be determined. table 23. examples for ?eld processing subject field sequence frame/?eld example 1 [1] example 2 [2] [3] example 3 [2] [4] [5] example 4 [2] [4] [6] 1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2 processed by task a a a bababbabbab bab ba state of detected itu 656 fid 0 1 0 01010101010 101 01 toggle ?ag 1 0 1 11001011000 [7] 111 [7] 00 bit 6 of sav/eav byte 0 1 0 01011011000 [7] 111 [7] 00 required sequence conversion at the vertical scaler [8] up up lo lo up up up up lo lo up up lo lo up lo lo up up lo lo lo up up lo up up up lo lo up lo lo lo up up lo up output [9] o o o oooooooooonooonooo h-scale ratio output pixel input pixel -------------------------------- = h-scale ratio 1 xpsc 5 : 0 [] ---------------------------- - 1024 xscy 12 : 0 [] ------------------------------- - =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 69 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.3.2.1 horizontal prescaler (subaddresses a0h to a7h and d0h to d7h) the prescaling function consists of an fir anti-alias ?lter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass ?lter to balance the sharpness and aliasing effects. the fir pre?lter stage implements different low-pass characteristics to reduce the anti-alias for downscales in the range of 1 to 1 2 . a cif optimized ?lter is built-in, which reduces artefacts for cif output formats (to be used in combination with the prescaler set to 1 2 scale); see t ab le 24 . the function of the prescaler is de?ned by: ? an integer prescaling ratio xpsc[5:0] a0h[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 1 63 ? an averaging sequence length xacl[5:0] a1h[5:0] (equals 0 to 63); range 1 to 64 ? a dc gain renormalization xdcg[2:0] a2h[2:0]; 1 down to 1 128 ? the bit xc2_1[a2h[3]], which de?nes the weighting of the incoming pixels during the averaging process: C xc2_1 = 0 t 1 + 1... +1+1 C xc2_1 = 1 t 1 + 2... +2+1 the prescaler creates a prescale dependent fir low-pass, with up to 64 + 7 ?lter taps. the parameter xacl[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1 xpsc[5:0] . the user can therefore decide between signal bandwidth (sharpness impression) and alias. the equation for the xpsc[5:0] calculation is: where: ? the range is 1 to 63 ( value 0 is not allowed ) ? npix_in = number of input pixel, and ? npix_out = number of desired output pixel over the complete horizontal scaler the use of the prescaler results in a xacl[5:0] and xc2_1 dependent gain ampli?cation. the ampli?cation can be calculated according to the equation: dc gain = [(xacl[5:0] - xc2_1) + 1] (xc2_1 + 1) it is recommended to use sequence lengths and weights, which results in a 2 n dc gain ampli?cation, as these amplitudes can be renormalized by the xdcg[2:0] controlled shifter of the prescaler. the renormalization range of xdcg[2:0] is 1, 1 2 down to 1 128 . xpsc 5 : 0 [] lower integer of npix _ in npix _ out ------------------------ = 1 2 n ------
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 70 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec other ampli?cations have to be normalized by using the following bcs control circuitry. in these cases the prescaler has to be set to an overall gain of 1, e.g. for an accumulation sequence of 1+1+1 (xa cl[5:0] = 2 and xc2_1 = 0), xdcg[2:0] must be set to 010, this equals 1 4 and the bcs has to amplify the signal to 4 3 (satn[7:0] and cont[7:0] value = lower integer of 4 3 64). the use of xacl[5:0] is xpsc[5:0] dependent. xacl[5:0] must be < 2 xpsc[5:0]. xacl[5:0] can be used to ?nd a compromise between bandwidth (sharpness) and alias effects. remark : due to bandwidth considerations xpsc[5:0] and xacl[5:0] can be chosen differently to the previously mentioned equations or t ab le 25 , as the horizontal phase scaling is able to scale in the range from zooming up by factor 3 to downscaling by a factor of 1024 8191 . figure 38 and figure 39 show some resulting frequency characteristics of the prescaler. t ab le 25 shows the recommended prescaler programming. other programming, other than given in t ab le 25 , may result in better alias suppression, but the resulting dc gain ampli?cation needs to be compensated by the bcs control, according to the equation: where: ? 2 xdcg[2:0] 3 dc gain ? dc gain = [(xacl[5:0] - xc2_1) + 1] (xc2_1 + 1) for example, if xacl[5:0] = 5, xc2_1 = 1, then the dc gain = 10 and the required xdcg[2:0] = 4. the horizontal source acquisition timing and the prescaling ratio is identical for both the luminance path and chrominance path, but the fir ?lter settings can be de?ned differently in the two channels. fade-in and fade-out of the ?lters is achieved by copying an original source sample each as ?rst and last pixel after prescaling. figure 36 and figure 37 show the frequency characteristics of the selectable fir ?lters. table 24. fir pre?lter functions pfuv[1:0] a2h[7:6] and pfy[1:0] a2h[5:4] luminance ?lter coef?cients chrominance coef?cients 00 bypassed bypassed 01 121 121 10 - 1 1 1.75 4.5 1.75 1 - 1 381083 11 12221 12221 cont 7 : 0 [] satn 7 : 0 [] lower integer of 2 xdcg 2 : 0 [] dc gain 64 ---------------------------------- - ==
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 71 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 36. luminance pre?lter characteristic fig 37. chrominance pre?lter characteristic mhb543 f_sig/f_clock 0 0.5 0.4 0.2 0.3 0.1 0.45 0.35 0.15 0.25 0.05 - 18 - 21 - 24 - 27 - 30 - 33 - 36 - 39 - 6 - 9 - 12 - 15 6 3 0 - 3 v (db) - 42 (3) (2) (1) (1) pfy[1:0] = 01. (2) pfy[1:0] = 10. (3) pfy[1:0] = 11. mhb544 (3) (2) (1) (1) pfuv[1:0] = 01. (2) pfuv[1:0] = 10. (3) pfuv[1:0] = 11. f_sig/f_clock 0 0.25 0.20 0.10 0.15 0.05 0.225 0.175 0.075 0.125 0.025 - 18 - 21 - 24 - 27 - 30 - 33 - 36 - 39 - 6 - 9 - 12 - 15 6 3 0 - 3 v (db) - 42
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 72 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec xc2_1 = 0; zeros at with xacl = (1), (2), (3), (4) or (5) fig 38. examples for prescaler ?lter characteristics: effect of increasing xacl[5:0] mhb545 (3) (4) (5) (2) (1) f_sig/f_clock 0 0.5 0.4 0.2 0.3 0.1 0.45 0.35 0.15 0.25 0.05 - 18 - 21 - 24 - 27 - 30 - 33 - 36 - 39 - 6 - 9 - 12 - 15 6 3 0 - 3 v (db) - 42 fn 1 xacl 1 + ------------------------ - = fig 39. examples for prescaler ?lter characteristics: setting xc2_1 mhb546 (3) (4) (5) (6) (2) (1) 3 db at 0.25 6 db at 0.33 (1) xc2_1 = 0 and xacl[5:0] = 1. (2) xc2_1 = 1 and xacl[5:0] = 2. (3) xc2_1 = 0 and xacl[5:0] = 3. (4) xc2_1 = 1 and xacl[5:0] = 4. (5) xc2_1 = 0 and xacl[5:0] = 7. (6) xc2_1 = 1 and xacl[5:0] = 8. f_sig/f_clock 0 0.5 0.4 0.2 0.3 0.1 0.45 0.35 0.15 0.25 0.05 - 18 - 21 - 24 - 27 - 30 - 33 - 36 - 39 - 6 - 9 - 12 - 15 6 3 0 - 3 v (db) - 42
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 73 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] resulting fir function. 9.3.2.2 horizontal ?ne scaling (variable phase delay ?lter; subaddresses a8h to afh and d8h to dfh) the horizontal ?ne scaling (vpd) should operate at scaling ratios between 1 2 and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from 1 7.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. in combination with the prescaler a compromise between sharpness impression and alias can be found. this is signal source and application dependent. for the luminance channel a ?lter structure with 10 taps is implemented, for the chrominance a ?lter with 4 taps. table 25. example of xacl[5:0] usage prescale ratio xpsc [5:0] recommended values fir pre?lter pfy[1:0]/ pfuv[1:0] for lower bandwidth requirements for higher bandwidth requirements xacl[5:0] xc2_1 xdcg[2:0] xacl[5:0] xc2_1 xdcg[2:0] 110000000to2 1 2 22121010to2 (1 2 1) 1 4 [1] (1 1) 1 2 [1] 1 3 34133022 (12221) 1 8 [1] (1111) 1 4 [1] 1 4 47034132 (11111111) 1 8 [1] (12221) 1 8 [1] 1 5 58147032 (122222221) 1 16 [1] (11111111) 1 8 [1] 1 6 68147033 (122222221) 1 16 [1] (11111111) 1 8 [1] 1 7 78147033 (122222221) 1 16 [1] (11111111) 1 8 [1] 1 8 815048143 (1111111111111111) 1 16 [1] (122222221) 1 16 [1] 1 9 915048143 (1111111111111111) 1 16 [1] (122222221) 1 16 [1] 1 10 10 16 1 5 8 1 4 3 (12222222222222221) 1 32 [1] (122222221) 1 16 [1] 1 13 13 16 1 5 16 1 5 3 1 15 15 31 0 5 16 1 5 3 1 16 16 31 0 5 16 1 5 3 1 19 19 32 1 6 32 1 6 3 1 31 31 32 1 6 32 1 6 3 1 32 32 63 1 7 32 1 6 3 1 35 35 63 1 7 63 1 7 3
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 74 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec luminance and chrominance scale increments (xscy[12:0] a9h[4:0] a8h[7:0] and xscc[12:0] adh[4:0] ach[7:0]) are de?ned independently, but must be set in a 2 : 1 relationship in the actual data path implementation. the phase offsets xphy[7:0] aah[7:0] and xphc[7:0] aeh[7:0] can be used to shift the sample phases slightly. xphy[7:0] and xphc[7:0] covers the phase offset range 7.999t to 1 32 t. the phase offsets should also be programmed in a 2 : 1 ratio. the underlying phase controlling dto has a 13-bit resolution. according to the equations: and the vpd covers the scale range from 0.125 to zoom 3.5. vpd acts equivalent to a polyphase ?lter with 64 possible phases. in combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer downscaled input picture. 9.3.3 vertical scaling the vertical scaler of the SAA7108AE; saa7109ae decoder part consists of a line fifo buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 1 64 . the vertical scaler is located between the bcs and horizontal ?ne scaler, so that the bcs can be used to compensate the dc gain ampli?cation of the acm mode (see section 9.3.3.2 ) as the internal rams are only 8-bit wide. 9.3.3.1 line fifo buffer (subaddresses 91h, b4h and c1h, e4h) the line fifo buffer is a dual ported ram structure for 768 pixels, with asynchronous write and read access. the line buffer can be used for various functions, but not all functions may be available simultaneously. the line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. for zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. for conversion of a 4:2:0 or 4:1:0 input sampling scheme (mpeg, video phone, indeo yuv-9) to itu like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being re?lled again by the source. it has to be preserved by means of the input acquisition window de?nition, so that the processing starts with a line containing luminance and chrominance information for 4:2:0and4:1:0 input. the bits fsc[2:1] 91h[2:1] de?ne the distance between the y/c lines. in the event of 4:2:2 and 4:1:1 fsc2 and fsc1 have to be set to 00. the line buffer can also be used for mirroring, i.e. for ?ipping the image left to right, for the vanity picture in video phone applications (bit ymir[b4h[4]]). in mirror mode only one active prescaled line can be held in the fifo at a time. the line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port. xscy 12 : 0 [] 1024 npix _ in xpsc 5 : 0 [] ---------------------------- - 1 npix _ out ------------------------ = xscc 12 : 0 [] xscy 12 : 0 [] 2 ------------------------------- - =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 75 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.3.3.2 vertical scaler (subaddresses b0h to bfh and e0h to efh) vertical scaling of any ratio from 64 (theoretical zoom) to 1 63 (icon) can be applied. the vertical scaling block consists of another line delay, and the vertical ?lter structure, that can operate in two different modes; linear phase interpolation (lpi) and accumulation (acm) mode. these are controlled by ymode[b4h[0]]: ? lpi mode : in the lpi mode (ymode = 0) two neighboring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. this linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. it interpolates between two consecutive input lines only. the lpi mode should be applied for scaling ratios around 1 (down to 1 2 ), it must be applied for vertical zooming . ? acm mode : the vertical acm mode (ymode = 1) represents a vertical averaging window over multiple lines, sliding over the ?eld. this mode also generates phase correct output lines. the averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. acm can be applied for downscales only from ratio 1 down to 1 64 . acm results in a scale dependent dc gain ampli?cation , which has to be precorrected by the bcs control of the scaler part. the phase and scale controlling dto calculates in 16-bit resolution, controlled by parameters yscy[15:0] b1h[7:0] b0h[7:0] and yscc[15:0] b3h[7:0] b2h[7:0], continuously over the entire ?eld. a start offset can be applied to the phase processing by means of the parameters ypy3[7:0] to ypy0[7:0] in bfh[7:0] to bch[7:0] and ypc3[7:0] to ypc0[7:0] in bbh[7:0] to b8h[7:0]. the start phase covers the range of 255 32 to 1 32 lines offset. by programming appropriate, opposite, vertical start phase values (subaddresses b8h to bfh and e8h to efh) depending on odd or even ?eld id of the source video stream and a or b page cycle, frame id conversion and ?eld rate conversion are supported (i.e. de-interlacing, re-interlacing). figure 40 and figure 41 and t ab le 26 and t ab le 27 describe the use of the offsets. remark: the vertical start phase, as well as the scaling ratio are de?ned independently for the luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4:2:2 output processing. the vertical processing communicates on its input side with the line fifo buffer. the scale related equations are: ? scaling increment calculation for acm and lpi mode, downscale and zoom: yscy[15:0] and yscc[15:0] = lower integer of ? bcs value to compensate dc gain in acm mode (contrast and saturation have to be set): cont[7:0] a5h[7:0] respectively satn[7:0] a6h[7:0] = lower integer of , or = lower integer of 1024 nline _ in nline _ out -------------------------- ? ?? nline _ out nline _ in -------------------------- 64 ? ?? 1024 yscy 15 : 0 [] ------------------------------- 64 ? ??
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 76 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.3.3.3 use of the vertical phase offsets as described in section 9.3.1.3 , the scaler processing may run randomly over the interlaced input sequence. additionally the interpretation and timing between itu 656 ?eld id and real-time detection by means of the state of h-sync at the falling edge of v-sync may result in different ?eld id interpretation. a vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input ?elds are processed, without regard to the actual scale at the starting point of operation (see figure 40 ). four events should be considered, they are illustrated in figure 41 . in t ab le 26 and t ab le 27 pho is a usable common phase offset. it should be noted that the equations of figure 41 produce an interpolated output, also for the unscaled case, as the geometrical reference position for all conversions is the position of the ?rst line of the lower ?eld; see t ab le 26 . if there is no need for up-lo and lo-up conversion and the input ?eld id is the reference for the back-end operation, then it is up-lo = up-up and lo-up = lo-lo and the 1 2 line phase shift (pho + 16) that can be skipped. this case is listed in t ab le 27 . the SAA7108AE; saa7109ae supports 4 phase offset registers per task and component (luminance and chrominance). the value of 20h represents a phase shift of one line. the registers are assigned to the following events; e.g. subaddresses b8h to bbh: ? b8h: 00 = input ?eld id 0, task status bit 0 (toggle status; see section 9.3.1.3 ) ? b9h: 01 = input ?eld id 0, task status bit 1 ? bah: 10 = input ?eld id 1, task status bit 0 ? bbh: 11 = input ?eld id 1, task status bit 1 depending on the input signal (interlaced or non-interlaced) and the task processing 50 hz or ?eld reduced processing with one or two tasks (see examples in section 9.3.1.3 ), other combinations may also be possible, but the basic equations are the same.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 77 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 40. basic problem of interlaced vertical scaling (example: downscale 3 5 ) mhb547 mismatched vertical line distances scale dependent start offset correct scale dependent position unscaled input scaled output, no phase offset scaled output, with phase offset field 1 field 2 field 1 field 2 field 1 field 2 offset = = 32 = 1 line shift a = input line shift = 16 b = input line shift + scale increment = c = scale increment + d = no offset = 0 fig 41. derivation of the phase related equations (example: interlace vertical scaling down to 3 5 , with ?eld conversion) mhb548 field 1 field 2 upper lower field 1 field 2 case up-up case lo-lo field 1 field 2 case up-lo case lo-up a b c d 1024 32 ----------- - 1 2 -- - 1 2 -- - 1 2 -- - yscy[15:0] 64 ---------------------------- - 16 + 1 2 -- - yscy[15:0] 64 ---------------------------- -
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 78 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] case 1: ofidc[90h[6]] = 0; scaler input ?eld id as output id; back-end interprets output ?eld id at logic 0 as upper output lines. [2] case 2: ofidc[90h[6]] = 1; task status bit as output id; back-end interprets output ?eld id at logic 0 as upper output lines. [3] case 3: ofidc[90h[6]] = 1; task status bit as output id; back-end interprets output ?eld id at logic 1 as upper output lines. 9.4 vbi data decoder and capture (subaddresses 40h to 7fh) the SAA7108AE; saa7109ae contains a versatile vbi data decoder. the implementation and programming model is in accordance with the vbi data slicer built into the multimedia video data acquisition circuit saa5284. the circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. the result is buffered into a dedicated vbi data fifo with a capacity of 2 56 bytes (2 14 double words). the clock frequency, signal source, ?eld frequency and accepted error count must be de?ned in subaddress 40h. table 26. examples for vertical phase offset usage: global equations input ?eld under processing output ?eld interpretation used abbreviation equation for phase offset calculation (decimal values) upper input lines upper output lines up-up pho + 16 upper input lines lower output lines up-lo lower input lines upper output lines lo-up pho lower input lines lower output lines lo-lo table 27. vertical phase offset usage; assignment of the phase offsets detected input ?eld id task status bit vertical phase offset case equation to be used 0 = upper lines 0 ypy0[7:0] and ypc0[7:0] case 1 [1] up-up (pho) case 2 [2] up-up case 3 [3] up-lo 0 = upper lines 1 ypy1[7:0] and ypc1[7:0] case 1 up-up (pho) case 2 up-lo case 3 up-up 1 = lower lines 0 ypy2[7:0] and ypc2[7:0] case 1 lo-lo case 2 lo-up case 3 lo-lo 1 = lower lines 1 ypy3[7:0] and ypc3[7:0] case 1 lo-lo case 2 lo-lo case 3 lo-up pho yscy 15 : 0 [] 64 ------------------------------- 16 ++ pho yscy 15 : 0 [] 64 ------------------------------- + pho yscy 15 : 0 [] 64 ------------------------------- 16 C + ? ?? pho yscy 15 : 0 [] 64 ------------------------------- 16 C + ? ??
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 79 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the supported vbi data standards are shown in t ab le 28 . for lines 2 to 24 of a ?eld, per vbi line, 1 of 16 standards can be selected (lcr24_[7:0] to lcr2_[7:0] in 57h[7:0] to 41h[7:0]: 23 2 4 bit programming bits). the de?nition for line 24 is valid for the rest of the corresponding ?eld, normally no text data (video data) should be selected there (lcr24_[7:0] = ffh) to stop the activity of the vbi data slicer during active video. to adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available: parameters hoff[10:0] 5bh[2:0] 59h[7:0], voff[8:0] 5bh[4] 5ah[7:0] and foff[5bh[7]]. contrary to the scalers counting, the slicers offsets de?ne the position of the horizontal and vertical trigger events related to the processed video ?eld. the trigger events are the falling edge of href and the falling edge of v123 from the decoder processing part. the relationship of these programming values to the input signal and the recommended values are given in figure 31 and figure 32 . table 28. data types supported by the data slicer block dt[3:0] 62h[3:0] standard type data rate (mbit/s) framing code (fc) fc window hamming check 0000 teletext eurowst, ccst 6.9375 27h wst625 always 0001 european closed caption 0.500 001 cc625 0010 vps 5 9951h vps 0011 wide screen signalling bits 5 1e 3c1fh wss 0100 us teletext (wst) 5.7272 27h wst525 always 0101 us closed caption (line 21) 0.503 001 cc525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text optional 1001 vitc/ebu time codes (europe) 1.8125 programmable vitc625 1010 vitc/smpte time codes (usa) 1.7898 programmable vitc525 1011 reserved 1100 us nabts 5.7272 programmable nabts optional 1101 moji (japanese) 5.7272 programmable (a7h) japtext 1110 japanese format switch (l20/22) 5 programmable open 1111 no sliced data transmitted (video data selected) 5 none disable
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 80 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.5 image port output formatter (subaddresses 84h to 87h) the output interface consists of a fifo for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the i port and a decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data stream and the accompanied reference and supporting information. the clock for the output interface can be derived from an internal clock, decoder, expansion port or an externally provided clock which is appropriate for e.g. vga and frame buffer. the clock can be up to 33 mhz. the scaler provides the following video related timing reference events (signals), which are available on pins as de?ned by subaddresses 84h and 85h: ? output ?eld id ? start and end of vertical active video range ? start and end of active video line ? data quali?er or gated clock ? actually activated programming page (if conlh is used) ? threshold controlled fifo ?lling ?ags (empty, full and ?lled) ? sliced data marker the discontinuous data stream at the scaler output is accompanied by a data valid ?ag (or data quali?er), or is transported via a gated clock. clock cycles with invalid data on the i port data bus (including the hpd pins in 16-bit output mode) are marked with code 00h. the output interface also arbitrates the transfer between scaled video data and sliced text data over the i port output. the bits vitx1 and vitx0 (subaddress 86h) are used to control the arbitration. as a further operation the serialization of the internal 32-bit double words to 8-bit or optional 16-bit output, as well as the insertion of the extended itu 656 codes (sav/eav for video data, anc or sav/eav codes for sliced text data) are done here. for handshake with the vga controller, or other memory or bus interface circuitry, programmable fifo ?ags are provided; see section 9.5.2 . 9.5.1 scaler output formatter (subaddresses 93h and c3h) the output formatter organizes the packing into the output fifo. the following formats are available: y-c b -c r 4:2:2, y-c b -c r 4:1:1, y-c b -c r 4:2:0, y-c b -c r 4:1:0 and y only (e.g. for raw samples). the formatting is controlled by fsi[2:0] 93h[2:0], foi[1:0] 93h[4:3] and fysk[93h[5]]. the data formats are de?ned on double words, or multiples, and are similar to the video formats as recommended for pci multimedia applications (compares to saa7146a), but planar formats are not supported. fsi[2:0] de?nes the horizontal packing of the data, foi[1:0] de?nes how many y only lines are expected, before a y/c line will be formatted. if fysk is set to logic 0 preceding y only lines will be skipped, and the output will always start with a y/c line.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 81 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec additionally the output formatter limits the amplitude range of the video data (controlled by illv[85h[5]]); see t ab le 31 . 9.5.2 video fifo (subaddress 86h) the video fifo at the scaler output contains 32 double words. that corresponds to 64 pixels in 16-bit y-c b -c r 4:2:2 for mat. but as the entire scaler can act as a pipeline buffer, the actual available buffer capacity for the image port is much higher, and can exceed beyond a video line. the image port and the video fifo, can operate with the video source clock (synchronous mode) or with an externally provided clock (asynchronous and burst mode), as appropriate for the vga controller or attached frame buffer. the video fifo provides 4 internal ?ags, reporting to what extent the fifo is actually ?lled. these are: ? the fifo almost empty (fae) ?ag ? the fifo combined flag (fcf) or fifo ?lled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark ? the fifo almost full (faf) ?ag ? the fifo over?ow (fovl) ?ag the trigger levels for fae and faf are programmable by ffl[1:0] 86h[3:2] (16, 24, 28, full) and fel[1:0] 86h[1:0] (16, 8, 4, empty). the state of this ?ag can be seen on pins igp0 or igp1. the pin mapping is de?ned by subaddresses 84h and 85h; see section 10.5 . table 29. byte stream for different output formats output format byte sequence for 8-bit output modes y- c b -c r 4:2:2 c b 0y0c r 0y1c b 2y2c r 2y3c b 4y4c r 4y5 c b 6y6 y- c b -c r 4:1:1 c b 0y0c r 0y1c b 4y2c r 4y3y4 y5y6 y7 c b 8y8 y only y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 table 30. explanation to t ab le 29 name explanation c b nc b (b - y) color difference component, pixel number n = 0, 2, 4 to 718 yn y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 c r nc r (r - y) color difference component, pixel number n = 0, 2, 4 to 718 table 31. limiting range on i port limit step illv[85h[5]] valid range suppressed codes (hexadecimal value) decimal value hexadecimal value lower range upper range 0 1 to 254 01 to fe 00 ff 1 8 to 247 08 to f7 00 to 07 f8 to ff
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 82 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.5.3 text fifo the data of the internal vbi data slicer is collected in the text fifo before the transmission over the i port is requested (normally before the video window starts). it is partitioned into two fifo sections. a complete line is ?lled into the fifo before a data transfer is requested. so normally, one line of text data is ready for transfer, while the next text line is collected. thus sliced text data is delivered as a block of quali?ed data, without any quali?cation gaps in the byte stream of the i port. the decoded vbi data is collected in the dedicated vbi data fifo. after the capture of a line has been completed, the fifo can be streamed through the image port, preceded by a header, giving line number and standard. the vbi data period can be signalled via the sliced data ?ag on pin igp0 or igp1. the decoded vbi data is lead by the itu ancillary data header (did[5:0] 5dh[5:0] at value < 3eh) or by sav/eav codes selectable by did[5:0] at value 3eh or 3fh. pin igp0 or igp1 is set if the ?rst byte of the anc header is valid on the i port bus. it is reset if an sav occurs. so it may frame multiple lines of text data output, in the event that the video processing starts with a distance of several video lines to the region of text data. valid sliced data from the text fifo is available on the i port as long as the igp0 or igp1 ?ag is set and the data quali?er is active on pin idq. the decoded vbi data is presented in two different data formats, controlled by bit recode. ? recode = 1: values 00h and ffh will be recoded to even parity values 03h and fch ? recode = 0: values 00h and ffh may occur in the data stream as detected 9.5.4 video and text arbitration (subaddress 86h) sliced text data and scaled video data are transferred over the same bus, the i port. the mixed transfer is controlled by an arbitration circuit. if the video data is transferred without any interrupt and the video fifo does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the blanking interval of the video. 9.5.5 data stream coding and reference signal generation (subaddresses 84h, 85h and 93h) as horizontal and vertical reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. as an alternative to the gates, the horizontal and vertical trigger pulses are generated on the rising edges of the gates. due to the dynamic fifo behavior of the complete scaler path, the output signal timing has no ?xed timing relationship to the real-time input video stream. so ?xed propagation delays, in terms of clock cycles, related to the analog input cannot be de?ned. the data stream is accompanied by a data quali?er. additionally invalid data cycles are marked with code 00h. if itu 656 like codes are not required, they can be suppressed in the output stream.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 83 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec as a further option, it is possible to provide the scaler with an external gating signal on pin itrdy. thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. the sketched reference signals and events can be mapped to the i port output pins idq, igph, igpv, igp0 and igp1. for ?exible use the polarities of all the outputs can be modi?ed. the default polarity for the quali?er and reference signals is logic 1 (active). t ab le 32 shows the relevant and supported sav and eav coding. [1] the leading byte sequence is: ffh-00h-00h. [2] the msb of the sav/eav code byte is controlled by: a) scaler output data: task a t msb = conlh[90h[7]]; task b t msb = conlh[c0h[7]]. b) vbi data slicer output data: did[5:0] 5dh[5:0] = 3eh t msb = 1; did[5:0] 5dh[5:0] = 3fh t msb = 0. table 32. sav/eav codes on the i port event description sav/eav codes on i port [1] (hexadecimal) comment msb [2] of sav/eav byte = 0 msb [2] of sav/eav byte = 1 field id = 0 field id = 1 field id = 0 field id = 1 next pixel is first pixel of any active line 0e 49 80 c7 href = active; vref = active previous pixel was last pixel of any active line, but not the last 13 54 9d da href = inactive; vref = active next pixel is first pixel of any v-blanking line 25 62 ab ec href = active; vref = inactive previous pixel was last pixel of the last active line or of any v-blanking line 38 7f b6 f1 href = inactive; vref = inactive no valid data, do not capture and do not increment pointer 00 idq pin inactive
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 84 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] inverted ep (bit 7); for ep see t ab le note 2 . [2] even parity (bit 6) of bits 5 to 0. [3] odd parity (bit 7) of bits 6 to 0. anc header active for did (subaddress 5dh) < 3eh fig 42. sliced data formats on the i port in 8-bit mode mhb549 00 00 ff 00 00 sav sdid dc idi1 idi2 d 1_3 d 1_4 d2_1 d dc_3 d dc_4 cs bc ff 00 00 eav 00 00 ... ... ... ... d 1_2 d 1_1 ... ff 00 00 eav 00 ff ff did sdid dc idi1 idi2 d 1_3 d 1_4 d dc_3 d dc_4 cs bc 00 00 ... anc header internal header sliced data anc data output is only filled up to the dword boundary timing reference code invalid data or end of raw vbi line timing reference code internal header sliced data invalid data and filling data table 33. explanation to figure 42 name explanation sav start of active data; see t ab le 34 sdid sliced data identi?cation: nep [1] , ep [2] , sdid5 to sdid0, freely programmable via i 2 c-bus subaddress 5eh, bits 5 to 0, e.g. to be used as source identi?er dc double word count: nep [1] , ep [2] , dc5 to dc0. dc describes the number of succeeding 32-bit words: for sav/eav mode dc is ?xed to 11 double words (byte value 4bh) for anc mode it is: dc = 1 4 (c + n), where c = 2 (the two data identi?cation bytes idi1 and idi2) and n = number of decoded bytes according to the chosen text standard it should be noted that the number of valid bytes inside the stream can be seen in the bc byte. idi1 internal data identi?cation 1: op [3] , fid (?eld 1 = 0, ?eld 2 = 1), linenumber8 to linenumber3 = double word 1 byte 1; see t ab le 34 idi2 internal data identi?cation 2: op [3] , linenumber2 to linenumber0, datatype3 to datatype0 = double word 1 byte 2; see t ab le 34 d n_m double word number n , byte number m d dc_4 last double word byte 4; remark: for sav/eav framing dc is ?xed to 0bh, missing data bytes are ?lled up; the ?ll value is a0h cs the check sum byte, the check sum is accumulated from the sav (respectively did) byte to the d dc_4 byte bc number of valid sliced bytes counted from the idi1 byte eav end of active data; see t ab le 34
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 85 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] nep = inverted ep; see t ab le note 2 . [2] ep = even parity of bits 5 to 0. [3] fid = 0: ?eld 1; fid = 1: ?eld 2. [4] i1 = 0 and i0 = 0: before line 1; i1 = 0 and i0 = 1: lines 1 to 23; i1 = 1 and i0 = 0: after line 23; i1 = 1 and i0 = 1: line 24 to end of ?eld. [5] subaddress 5dh at 3eh and 3fh are used for itu 656 like sav/eav header generation; recommended value. [6] v = 0: active video; v = 1: blanking. [7] h = 0: start of line; h = 1: end of line. [8] dc = data count in double words according to the data type. [9] op = odd parity of bits 6 to 0. [10] ln = line number. [11] dt = data type according to t ab le 28 . 9.6 audio clock generation (subaddresses 30h to 3fh) the SAA7108AE; saa7109ae incorporates the generation of a ?eld-locked audio clock as an auxiliary function for video capture. an audio sample clock, that is locked to the ?eld frequency, ensures that there is always the same prede?ned number of audio samples associated with a ?eld, or a set of ?elds. this ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), mpeg or other compression, or non-linear editing. 9.6.1 master audio clock the audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. the master audio clock is de?ned by the parameters: ? audio master clocks per field, acpf[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to the equation: table 34. bytes stream of the data slicer nick name comment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 did, sav, eav subaddress 5dh = 00h nep [1] ep [2] 010fid [3] i1 [4] i0 [4] subaddress 5dh bit 5 = 1 nep [1] ep [2] 0 d4[5dh] d3[5dh] d2[5dh] d1[5dh] d0[5dh] subaddress 5dh bit 5 = 3eh [5] 1 fid [3] v [6] h [7] p3 p2 p1 p0 subaddress 5dh bit 5 = 3fh [5] 0 fid [3] v [6] h [7] p3 p2 p1 p0 sdid programmable via subaddress 5eh nep [1] ep [2] d5[5eh] d4[5eh] d3[5eh] d2[5eh] d1[5eh] d0[5eh] dc [8] nep [1] ep [2] dc5 dc4 dc3 dc2 dc1 dc0 idi1 op [9] fid [3] ln8 [10] ln7 [10] ln6 [10] ln5 [10] ln4 [10] ln3 [10] idi2 op [9] ln2 [10] ln1 [10] ln0 [10] dt3 [11] dt2 [11] dt1 [11] dt0 [11] cs check sum byte cs6 cs6 cs5 cs4 cs3 cs2 cs1 cs0 bc valid byte count op [9] 0 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 acpf 17 : 0 [] round audio frequency field frequency -------------------------------------------- ? ?? =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 86 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec ? audio master clocks nominal increment, acni[21:0] 36h[5:0] 35h[7:0] 34h[7:0] according to the equation: see t ab le 35 for examples. remark : for standard applications the synthesized audio clock amclk can be used directly as master clock and as input clock for port amxclk (short cut) to generate asclk and alrclk. for high-end applications it is recommended to use an external analog pll circuit to enhance the performance of the generated audio clock. 9.6.2 signals asclk and alrclk two binary divided signals asclk and alrclk are provided for slower serial digital audio signal transmission and for channel-select. the frequencies of these signals are de?ned by the following parameters: ? sdiv[5:0] 38h[5:0] according to the equation: t ? lrdiv[5:0] 39h[5:0] according to the equation: t see t ab le 36 for examples. table 35. programming examples for audio master clock generation crystal frequency (mhz) field (hz) acpf acni decimal hex decimal hex amclk = 256 48 khz (12.288 mhz) 32.11 50 245760 3 c000 3210190 30 fbce 59.94 205005 3 20cd 3210190 30 fbce 24.576 50 ---- 59.94 ---- amclk = 256 44.1 khz (11.2896 mhz) 32.11 50 225792 3 7200 2949362 2d 00f2 59.94 188348 2 dfbc 2949362 2d 00f2 24.576 50 225792 3 7200 3853517 3a cccd 59.94 188348 2 dfbc 3853 517 3a cccd amclk = 256 32 khz (8.192 mhz) 32.11 50 163840 2 8000 2140127 20 a7df 59.94 136670 2 15de 2140127 20 a7df 24.576 50 163840 2 8000 2796203 2a aaab 59.94 136670 2 15de 2796203 2a aaab acni 21 : 0 [] round audio frequency crystal frequency ----------------------------------------------- - 2 23 ? ?? = f asclk f amxclk sdiv 1 + () 2 ------------------------------------- - = sdiv 5 : 0 [] f amxclk 2f asclk ----------------------- 1 C = f alrclk f asclk lrdiv 2 --------------------------- - = lrdiv 5 : 0 [] f asclk 2f alrclk ------------------------- =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 87 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.6.3 other control signals further control signals are available to de?ne reference clock edges and vertical references; see t ab le 37 . 10. input/output interfaces and ports of digital video decoder part the SAA7108AE; saa7109ae has 5 different i/o interfaces: ? analog video input interface, for analog cvbs and/or y and c input signals ? audio clock port ? digital real-time signal port (rt port) ? digital video expansion port (x port), for unscaled digital video input and output ? digital image port (i port) for scaled video data output and programming ? digital host port (h port) for extension of the image port or expansion port from 8-bit to 16-bit table 36. programming examples for asclk/alrclk clock generation amxclk (mhz) asclk (khz) sdiv alrclk (khz) lrdiv decimal hex decimal hex 12.288 1536 3 03 48 16 10 768 7 07 48 8 08 11.2896 1411.2 3 03 44.1 16 10 2822.4 1 01 44.1 32 10 8.192 1024 3 03 32 16 10 20481 01323210 table 37. control signals control signal description apll[3ah[3]] audio pll mode 0 = pll closed 1 = pll open amvr[3ah[2]] audio master clock vertical reference 0 = internal vertical reference 1 = external vertical reference lrph[3ah[1]] alrclk phase 0 = invert asclk, alrclk edges triggered by falling edge of asclk 1 = do not invert asclk, alrclk edges triggered by rising edge of asclk scph[3ah[0]] asclk phase 0 = invert amxclk, asclk edges triggered by falling edge of amxclk 1 = do not invert amxclk, asclk edges triggered by rising edge of amxclk
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 88 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 10.1 analog terminals the SAA7108AE; saa7109ae has 6 analog inputs ai21 to ai24, ai11 and ai12 (see t ab le 38 ) for composite video cvbs or s-video y/c signal pairs. additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. there are no peripheral components required other than these decoupling capacitors and 18 w /56 w termination resistors, one set per connected input signal; see also application example in figure 68 . two anti-alias ?lters are integrated, and self adjusting via the clock frequency. clamp and gain control for the two adcs are also integrated. an analog video output (pin aout) is provided for testing purposes. 10.2 audio clock signals the SAA7108AE; saa7109ae also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow pll. this ensures that the multimedia capture and compression processes always gather the same prede?ned number of samples per video frame. an audio master clock amclk and two divided clocks, asclk and alrclk, are generated; see t ab le 39 . ? asclk: can be used as audio serial clock ? alrclk: audio left/right channel clock the ratios are programmable; see section 9.6 . table 38. analog pin description symbol pin i/o description bit ai24 to ai21 p6, p7, p9 and p10 i analog video signal inputs, e.g. 2 cvbs signals and two y/c pairs can be connected simultaneously mode3 to mode0 ai12 and ai11 p11 and p13 i analog video signal inputs, e.g. 2 cvbs signals and two y/c pairs can be connected simultaneously mode3 to mode0 aout m10 o analog video output, for test purposes aosl1 and aosl0 ai1d and ai2d p12 and p8 i analog reference pins for differential adc operation -
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 89 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 10.3 clock and real-time synchronization signals for the generation of the line-locked video (pixel) clock llc, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. an oscillator is built-in for fundamental or third harmonic crystals. the supported crystal frequencies are 32.11 mhz or 24.576 mhz (de?ned during reset by strapping pin alrclk). alternatively pins xtalid and xtalie can be driven from an external single-ended oscillator. the crystal oscillation can be propagated as a clock to other ics in the system via pin xtoutd. the line-locked clock (llc) is the double pixel clock of nominal 27 mhz. it is locked to the selected video input, generating baseband video pixels according to itu recommendation 601 . in order to support interfacing circuits, a direct pixel clock (llc2) is also provided. the pins for line and ?eld timing reference signals are rtco, rts1 and rts0. various real-time status information can be selected for the rts pins. the signals are always available (output) and re?ect the synchronization operation of the decoder part in the SAA7108AE; saa7109ae. the function of the rts1 and rts0 pins can be de?ned by bits rtse1[3:0] 12h[7:4] and rtse0[3:0] 12h[3:0]; see t ab le 40 . table 39. audio clock pin description symbol pin i/o description bit amclk k12 o audio master clock output acpf[17:0] 32h[1:0] 31h[7:0] 30h[7:0] and acni[21:0] 36h[5:0] 35h[7:0] 34h[7:0] amxclk j12 i external audio master clock input for the clock division circuit, can be directly connected to output amclk for standard applications - asclk k14 o serial audio clock output, can be synchronized to rising or falling edge of amxclk sdiv[5:0] 38h[5:0] and scph[3ah[0]] alrclk j13 o audio channel (left/right) clock output, can be synchronized to rising or falling edge of asclk lrdiv[5:0] 39h[5:0] and lrph[3ah[1]] table 40. clock and real-time synchronization signals symbol pin i/o description bit crystal oscillator xtalid p2 i input for crystal oscillator or reference clock - xtalod p3 o output of crystal oscillator - xtoutd p4 o reference (crystal) clock output drive (optional) xtoute[14h[3]] real-time signals (rt port) llc m14 o line-locked clock, nominal 27 mhz, double pixel clock locked to the selected video input signal -
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 90 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 10.4 video expansion port (x port) the expansion port is intended for transporting video streams of image data from other digital video circuits such as mpeg encoder/decoder and video phone codec, to the image port (i port); see t ab le 41 . the expansion port consists of two groups of signals/pins: ? 8-bit data, i/o, regular components video y-c b -c r 4:2:2,i.e.c b -y-c r -y, byte serial, exceptionally raw video samples (e.g. adc test); in input mode the data bus can be extended to 16-bit by pins hpd7 to hpd0. ? clock, synchronization and auxiliary signals, accompanying the data stream, i/o as output, these are direct copies of the decoder signals. the data transfers through the expansion port represent a single d1 port, with half duplex mode. the sav and eav codes may be inserted optionally for data input (controlled by bit xcode[92h[3]]). the input/output direction is switched for complete ?elds only. llc2 l14 o line-locked pixel clock, nominal 13.5 mhz - rtco l13 o real-time control output, transfers real-time status information supporting rtc level 3.1 (see document how to use real time control (rtc) , available on request) - rts0 k13 o real-time status information line 0, can be programmed to carry various real-time information; see t ab le 160 rtse0[3:0] 12h[3:0] rts1 l10 o real-time status information line 1, can be programmed to carry various real-time information; see t ab le 161 rtse1[3:0] 12h[7:4] table 40. clock and real-time synchronization signals continued symbol pin i/o description bit table 41. signals dedicated to the expansion port symbol pin i/o description bit xpd7 to xpd0 k2, k3, l1 to l3, m1, m2 and n1 i/o x port data: in output mode controlled by decoder section, data format see t ab le 42 ; in input mode y-c b -c r 4 : 2 : 2 serial input data or luminance part of a 16-bit y- c b -c r 4 : 2 : 2 input ofts[2:0] 13h[2:0], 91h[7:0] and c1h[7:0] xclk m3 i/o clock at expansion port: if output, then copy of llc; as input normally a double pixel clock of up to 32 mhz or a gated clock (clock gated with a quali?er) xcks[92h[0]] xdq m4 i/o data valid ?ag of the expansion port input (quali?er): if output, then decoder (href and vgate) gate; see figure 35 - xrdy n3 o data request ?ag = ready to receive, to work with optional buffer in external device, to prevent internal buffer over?ow; second function: input related task ?ag a/b xrqt[83h[2]]
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 91 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 10.4.1 x port con?gured as output if the data output is enabled at the expansion port, then the data stream from the decoder is presented. the data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers lcr2 to lcr24; see t ab le 20 . in contrast to the image port, the sliced data format is not available on the expansion port. instead, raw cvbs samples are always transferred if any sliced data type is selected. some details of data types on the expansion port are as follows: ? active video (data type 15): contains component y-c b -c r 4:2:2 signal, 720 active pixels per line. the amplitude and offsets are programmable via dbri7 to dbri0, dcon7 to dcon0, dsat7 to dsat0, offu1, offu0, offv1 and offv0. the nominal levels are illustrated in figure 27 . ? test line (data type 6): is similar to the active video format, with some constraints within the data processing: C adaptive chrominance comb ?lter, vertical ?lter (chrominance comb ?lter for ntsc standards, pal phase error correction) within the chrominance processing are disabled C adaptive luminance comb ?lter, peaking and chrominance trap are bypassed within the luminance processing this data type is de?ned for future enhancements. it could be activated for lines containing standard test signals within the vertical blanking period. currently most sources do not contain test lines. the nominal levels are illustrated in figure 27 . ? raw samples (data types 0 to 5 and 7 to 14): c b -c r samples are similar to data type 6, but cvbs samples are transferred instead of processed luminance samples within the y time slots. the amplitude and offset of the cvbs signal is programmable via rawg7 to rawg0 and rawo7 to rawo0; see section 11 , t ab le 167 and t ab le 168 . the nominal levels are illustrated in figure 28 . the relationship of lcr programming to line numbers is described in section 9.2 , figure 31 and figure 32 . xrh n2 i/o horizontal reference signal for the x port: as output: href or hs from the decoder (see figure 35 ); as input: a reference edge for horizontal input timing and a polarity for input ?eld id detection can be de?ned xrhs[13h[6]], xfdh[92h[6]] and xdh[92h[2]] xrv l5 i/o vertical reference signal for the x port: as output: v123 or ?eld id from the decoder (see figure 33 and figure 34 ); as input: a reference edge for vertical input timing and for input ?eld id detection can be de?ned xrvs[1:0] 13h[5:4], xfdv[92h[7]] and xdv[1:0] 92h[5:4] xtri k1 i port control: switches x port input to 3-state xpe[1:0] 83h[1:0] table 41. signals dedicated to the expansion port continued symbol pin i/o description bit
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 92 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the data type selections by lcr are overruled by setting ofts2 = 1 (subaddress 13h bit 2). this setting is mainly intended for device production testing. the vpo-bus carries the upper or lower 8 bits of the two adcs depending on the ofts[1:0] 13h[1:0] settings; see t ab le 162 . the input con?guration is done via mode[3:0] 02h[3:0] settings; see t ab le 144 . if a y/c mode is selected, the expansion port carries the multiplexed output signals of both adcs, and in cvbs mode the output of only one adc. no timing reference codes are generated in this mode. remark : the lsbs (bit 0) of the adcs are also available on pin rts0; see t ab le 160 . the sav/eav timing reference codes de?ne the start and end of valid data regions. the itu-blanking code sequence - 80 - 10 - 80 - 10 -... is transmitted during the horizontal blanking period between eav and sav. the position of the f-bit is constant in accordance with itu 656; see t ab le 44 and t ab le 45 . the v-bit can be generated in two different ways (see t ab le 44 and t ab le 45 ) controlled via ofts1 and ofts0; see t ab le 162 . the f and v bits change synchronously with the eav code. [1] the generation of the timing reference codes can be suppressed by setting ofts[2:0] to 010; see t ab le 162 . in this event the code sequence is replaced by the standard - 80 - 10 - blanking values. [2] if raw samples or sliced data are selected by the line control registers (lcr2 to lcr24), the y samples are replaced by cvbs samples. table 42. data format on the expansion port blanking period timing reference code (hexadecimal) [1] 720 pixels y-c b -c r 4:2:2 data [2] timing reference code (hexadecimal) [1] blanking period ... 80 10 ff 00 00 sav c b 0y0c r 0y1c b 2 y2 ... c r 718 y719 ff 00 00 eav 80 10 ... table 43. sav/eav format on expansion port xpd7 to xpd0 bit symbol description 7 logic 1 6 f ?eld bit 1st ?eld: f = 0 2nd ?eld: f = 1 for vertical timing see t ab le 44 and t ab le 45 5 v vertical blanking bit vbi: v = 1 active video: v = 0 for vertical timing see t ab le 44 and t ab le 45 4 h format h = 0 in sav format h = 1 in eav format 3 to 0 p[3:0] reserved; evaluation not recommended (protection bits according to itu-r bt 656)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 93 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 10.4.2 x port con?gured as input if the data input mode is selected at the expansion port, then the scaler can select its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit scsrc[1:0] 91h[5:4]). byte serial y-c b -c r 4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external adc may be input (see also bits fsc[2:0] 91h[2:0]). the input data stream must be accompanied by an external clock (xclk), quali?er xdq and reference signals xrh and xrv. instead of the reference signal, embedded sav and eav codes according to itu 656 are also accepted. the protection bits are not evaluated. xrh and xrv carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. the ?eld id of the input video stream is carried in the phase (edge) of xrv and state of xrh, or directly as fs (frame sync, odd/even signal) on the xrv pin (controlled by xfdv[92h[7]], xfdh[92h[6]] and xdv[1:0] 92h[5:4]). table 44. 525 lines/60 hz vertical timing line number f (itu 656) v ofts[2:0] = 000 (itu 656) ofts[2:0] = 001 1 to 3 1 1 according to selected vgate position type via vsta and vsto (subaddresses 15h to 17h); see t ab le 164 to t ab le 166 4to19 0 1 20 0 0 21 0 0 22 to 261 0 0 262 0 0 263 0 0 264 and 265 0 1 266 to 282 1 1 283 1 0 284 1 0 285 to 524 1 0 525 1 0 table 45. 625 lines/50 hz vertical timing line number f (itu 656) v ofts[2:0] = 000 (itu 656) ofts[1:0] = 10 1 to 22 0 1 according to selected vgate position type via vsta and vsto (subaddresses 15h to 17h); see t ab le 164 to t ab le 166 23 0 0 24 to 309 0 0 310 0 0 311 and 312 0 1 313 to 335 1 1 336 1 0 337 to 622 1 0 623 1 0 624 and 625 1 1
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 94 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the trigger events on xrh (rising/falling edge) and xrv (rising/falling/both edges) for the scalers acquisition window are de?ned by xdv[1:0] 92h[5:4] and xdh[92h[2]]. the signal polarity of the quali?er can also be de?ned (bit xdq[92h[1]]). alternatively to a quali?er, the input clock can be applied to a gated clock (clock gated with a data quali?er, controlled by bit xcks[92h[0]]). in this event, all input data will be quali?ed. 10.5 image port (i port) the image port transfers data from the scaler as well as from the vbi data slicer, if selected (maximum 33 mhz). the reference clock is available at the iclk pin, as an output or as an input (maximum 33 mhz). as output, iclk is derived from the line-locked decoder or expansion port input clock. the data stream from the scaler output is normally discontinuous. therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) ?ag on pin idq. for pin constrained applications the idq pin can be programmed to function as a gated clock output (bit icks2[80h[2]]). the data formats at the image port are de?ned in double words of 32 bits (4 bytes), such as the related fifo structures. however, the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins hpd7 to hpd0 are used for chrominance data. the four bytes of the double words are serialized in words or bytes. available formats are as follows: ? y- c b -c r 4:2:2 ? y- c b -c r 4:1:1 ? raw samples ? decoded vbi data for handshake with the receiving vga controller, or other memory or bus interface circuitry, f, h and v reference signals and programmable fifo ?ags are provided. the information is provided on pins igp0, igp1, igph and igpv. the functionality on these pins is controlled via subaddresses 84h and 85h. vbi data is collected over an entire line in its own fifo and transferred as an uninterrupted block of bytes. decoded vbi data can be signed by the vbi ?ag on pin igp0 or igp1. as scaled video data and decoded vbi data may come from different and asynchronous sources, an arbitration scheme is needed. normally the vbi data slicer has priority. the image port consists of the pins and/or signals, as listed in t ab le 46 . for pin constrained applications, or interfaces, the relevant timing and data reference signals can also be encoded into the data stream. therefore the corresponding pins do not need to be connected. the minimum image port con?guration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. the inserted codes are de?ned in close relationship to the itu-r bt.656 (d1) recommendation, where possible. the following deviations from itu 656 recommendation are implemented at the SAA7108AE; saa7109aes image port interface: ? sav and eav codes are only present in those lines, where data is to be transferred, i.e. active video lines, or vbi raw samples, no codes for empty lines
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 95 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec ? there may be more or less than 720 pixels between sav and eav ? data content and number of clock cycles during horizontal and vertical blanking is unde?ned, and may not be constant ? data stream may be interleaved with not-valid data codes, 00h, but sav and eav 4-byte codes are not interleaved with not-valid data codes ? there may be an irregular pattern of not-valid data, or idq, and as a result, c b -y-c r -y is not in a ?xed phase to a regular clock divider ? vbi raw sample streams are enveloped with sav and eav, like normal video ? decoded vbi data is transported as ancillary (anc) data, two modes: C direct decoded vbi data bytes (8-bit) are directly placed in the anc data ?eld, 00h and ffh codes may appear in the data block (violation to itu-r bt.656) C recoded vbi data bytes (8-bit) directly placed in anc data ?eld, 00h and ffh codes will be recoded to even parity codes 03h and fch to suppress invalid itu-r bt.656 codes there are no empty cycles in the ancillary code and its data ?eld. the data codes 00h and ffh are suppressed (changed to 01h or feh respectively) in the active video stream, as well as in the vbi raw sample stream (vbi pass-through). optionally, the number range can be further limited. table 46. signals dedicated to the image port symbol pin i/o description bit ipd7 to ipd0 e14, d14, c14, b14, e13, d13, c13 and b13 o i port data icode[93h[7]], iswp[1:0] 85h[7:6] and ipe[1:0] 87h[1:0] iclk h12 i/o continuous reference clock at image port, can be input or output, as output decoder llc or xclk from x port icks[1:0] 80h[1:0] and ipe[1:0] 87h[1:0] idq h14 o data valid ?ag at image port, quali?er, with programmable polarity; secondary function: gated clock icks2[80h[2]], idqp[85h[0]] and ipe[1:0] 87h[1:0] igph g12 o horizontal reference output signal, copy of the horizontal gate signal of the scaler, with programmable polarity; alternative function: hreset pulse idh[1:0] 84h[1:0], irhp[85h[1]] and ipe[1:0] 87h[1:0] igpv f13 o vertical reference output signal, copy of the vertical gate signal of the scaler, with programmable polarity; alternative function: vreset pulse idv[1:0] 84h[3:2], irvp[85h[2]] and ipe[1:0] 87h[1:0] igp1 g13 o general purpose output signal for i port idg12[86h[4]], idg1[1:0] 84h[5:4], ig1p[85h[3]] and ipe[1:0] 87h[1:0] igp0 f14 o general purpose output signal for i port idg02[86h[5]], idg0[1:0] 84h[7:6], ig0p[85h[4]] and ipe[1:0] 87h[1:0] itrdy j14 i target ready input signals - itri g14 i port control, switches i port into 3-state ipe[1:0] 87h[1:0]
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 96 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 10.6 host port for 16-bit extension of video data i/o (h port) the h port pins hpd can be used for extension of the data i/o paths to 16-bit. the i port has functional priority. if i8_16[93h[6]] is set to logic 1 the output drivers of the h port are enabled depending on the i port enable control. for i8_16 = 0, the hpd output is disabled. 10.7 basic input and output timing diagrams for the i and x ports 10.7.1 i port output timing figure 43 to figure 49 illustrate the output timing via the i port. igph and igpv are logic 1 active gate signals. if reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. valid data is accompanied by the output data quali?er on pin idq. in addition, invalid cycles are marked with output code 00h. the idq output pin may be de?ned to be a gated clock output signal (iclk and internal idq). 10.7.2 x port input timing at the x port the input timing requirements are the same as those for the i port output. but different to those below: ? it is not necessary to mark invalid cycles with a 00h code ? no constraints on the input quali?er (can be a random pattern) ? xclk may be a gated clock (xclk and external xdq) remark : all timings illustrated in figure 43 to figure 49 are given for an uninterrupted output stream (no handshake with the external hardware). table 47. signals dedicated to the host port symbol pin i/o description bit hpd7 to hpd0 a13, d12, c12, b12, a12, c11, b11 and a11 i/o 16-bit extension for digital i/o (chrominance component) ipe[1:0] 87h[1:0], itri[8fh[6]] and i8_16[93h[6]] fig 43. output timing i port for serial 8-bit data at start of a line (icode = 1) ipd [ 7:0 ] igph idq iclk 00 ff 00 00 sav 00 c b y c r y00 c b y c r y00 mhb550
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 97 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 44. output timing at the i port for serial 8-bit data at start of a line (icode = 0) ipd [ 7:0 ] igph idq iclk 00 c b y c r y00 c b y c r y00 mhb551 fig 45. output timing at the i port for serial 8-bit data at end of a line (icode = 1) ipd [ 7:0 ] igph idq iclk 00 c b y c r y00 c b y c r y00ff0000eav00 mhb552 fig 46. output timing at the i port for serial 8-bit data at end of a line (icode = 0) ipd [ 7:0 ] igph idq iclk 00 c b y c r y00 c b y c r y00 mhb553
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 98 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 47. output timing for 16-bit data output via the i port and the h port with codes (icode = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle ipd [ 7:0 ] hpd [ 7:0 ] igph idq iclk 00 ff 00 00 y0 y1 00 y2 y3 y n - 1 y n 00 ff 00 00 mhb554 00 00 sav 00 00 c b c b c r c r c r c b 00 00 eav 00 fig 48. horizontal and vertical gate output timing igpv igph idq mhb555 fig 49. output timing for sliced vbi data in 8-bit serial output mode (dotted graphs for sav/eav mode) mhb733 ipd [ 7:0 ] hpd [ 7:0 ] sliced data flag on igp0 or igp1 idq iclk 00 00 ff ff did sdid xx yy zz cs bc 00 00 00 00 ff 00 sav 00 00 00 bc ff eav
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 99 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11. i 2 c-bus description 11.1 digital video encoder part table 48. slave receiver bit allocation map (slave address 88h) register function subaddress (hexadecimal) d7 d6 d5 d4 d3 d2 d1 d0 status byte (read only) 00 ver2 ver1 ver0 ccrdo ccrde - fseq o_e null 01 to 15 [1] [1] [1] [1] [1] [1] [1] [1] common dac adjust ?ne 16 [1] [1] [1] [1] dacf3 dacf2 dacf1 dacf0 r dac adjust coarse 17 [1] [1] [1] rdacc4 rdacc3 rdacc2 rdacc1 rdacc0 g dac adjust coarse 18 [1] [1] [1] gdacc4 gdacc3 gdacc2 gdacc1 gdacc0 b dac adjust coarse 19 [1] [1] [1] bdacc4 bdacc3 bdacc2 bdacc1 bdacc0 msm threshold 1a msmt7 msmt6 msmt5 msmt4 msmt3 msmt2 msmt1 msmt0 monitor sense mode 1b msm msa msoe [1] [1] rcomp gcomp bcomp chip id (read only) 1c cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 wide screen signal 26 wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 wide screen signal 27 wsson [1] wss13 wss12 wss11 wss10 wss9 wss8 real-time control, burst start 28 [1] [1] bs5 bs4 bs3 bs2 bs1 bs0 sync reset enable, burst end 29 sres [1] be5 be4 be3 be2 be1 be0 copy generation 0 2a cg07 cg06 cg05 cg04 cg03 cg02 cg01 cg00 copy generation 1 2b cg15 cg14 cg13 cg12 cg11 cg10 cg09 cg08 cg enable, copy generation 2 2c cgen [1] [1] [1] cg19 cg18 cg17 cg16 output port control 2d vbsen cvbsen1 cvbsen0 cen encoff clk2en cvbsen2 [1] null 2e to 36 [1] [1] [1] [1] [1] [1] [1] [1] input path control 37 [1] yupsc yfil1 yfil0 [1] czoom igain xint gain luminance for rgb 38 [1] [1] [1] gy4 gy3 gy2 gy1 gy0 gain color difference for rgb 39 [1] [1] [1] gcd4 gcd3 gcd2 gcd1 gcd0 input port control 1 3a cbenb [1] syntv symp demoff csync y2c uv2c vps enable, input control 2 54 vpsen [1] gpval gpen [1] [1] edge slot vps byte 5 55 vps57 vps56 vps55 vps54 vps53 vps52 vps51 vps50 vps byte 11 56 vps117 vps116 vps115 vps114 vps113 vps112 vps111 vps110 vps byte 12 57 vps127 vps126 vps125 vps124 vps123 vps122 vps121 vps120 vps byte 13 58 vps137 vps136 vps135 vps134 vps133 vps132 vps131 vps130 vps byte 14 59 vps147 vps146 vps145 vps144 vps143 vps142 vps141 vps140 chrominance phase 5a chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 100 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec gain u 5b gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5c gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, black level 5d gainu8 [1] blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, blanking level 5e gainv8 [1] blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 ccr, blanking level vbi 5f ccrs1 ccrs0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60 [1] [1] [1] [1] [1] [1] [1] [1] standard control 61 downd downa inpi ygs [1] scbw pal fise burst amplitude 62 rtce bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63 fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66 fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67 l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68 l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69 l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6a l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 null 6b [1] [1] [1] [1] [1] [1] [1] [1] trigger control 6c htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6d htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6e nvtrig blckon phres1 phres0 ldel1 ldel0 flc1 flc0 closed caption, teletext enable 6f ccen1 ccen0 ttxen sccln4 sccln3 sccln2 sccln1 sccln0 active display window horizontal start 70 adwhs7 adwhs6 adwhs5 adwhs4 adwhs3 adwhs2 adwhs1 adwhs0 active display window horizontal end 71 adwhe7 adwhe6 adwhe5 adwhe4 adwhe3 adwhe2 adwhe1 adwhe0 msbs adwh 72 [1] adwhe10 adwhe9 adwhe8 [1] adwhs10 adwhs9 adwhs8 ttx request horizontal start 73 ttxhs7 ttxhs6 ttxhs5 ttxhs4 ttxhs3 ttxhs2 ttxhs1 ttxhs0 ttx request horizontal delay 74 [1] [1] [1] [1] ttxhd3 ttxhd2 ttxhd1 ttxhd0 csync advance 75 csynca4 csynca3 csynca2 csynca1 csynca0 [1] [1] [1] ttx odd request vertical start 76 ttxovs7 ttxovs6 ttxovs5 ttxovs4 ttxovs3 ttxovs2 ttxovs1 ttxovs0 ttx odd request vertical end 77 ttxove7 ttxove6 ttxove5 ttxove4 ttxove3 ttxove2 ttxove1 ttxove0 table 48. slave receiver bit allocation map (slave address 88h) continued register function subaddress (hexadecimal) d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 101 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec ttx even request vertical start 78 ttxevs7 ttxevs6 ttxevs5 ttxevs4 ttxevs3 ttxevs2 ttxevs1 ttxevs0 ttx even request vertical end 79 ttxeve7 ttxeve6 ttxeve5 ttxeve4 ttxeve3 ttxeve2 ttxeve1 ttxeve0 first active line 7a fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7b lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 ttx mode, msb vertical 7c ttx60 lal8 ttxo fal8 ttxeve8 ttxove8 ttxevs8 ttxovs8 null 7d [1] [1] [1] [1] [1] [1] [1] [1] disable ttx line 7e line12 line11 line10 line9 line8 line7 line6 line5 disable ttx line 7f line20 line19 line18 line17 line16 line15 line14 line13 fifo status (read only) 80 ---- iferr bferr ovfl udfl pixel clock 0 81 pcl07 pcl06 pcl05 pcl04 pcl03 pcl02 pcl01 pcl00 pixel clock 1 82 pcl15 pcl14 pcl13 pcl12 pcl11 pcl10 pcl09 pcl08 pixel clock 2 83 pcl23 pcl22 pcl21 pcl20 pcl19 pcl18 pcl17 pcl16 pixel clock control 84 dclk pclsy ifra ifbp pcle1 pcle0 pcli1 pcli0 fifo control 85 eidiv [1] [1] [1] fili3 fili2 fili1 fili0 null 86 to 8f [1] [1] [1] [1] [1] [1] [1] [1] horizontal offset 90 xofs7 xofs6 xofs5 xofs4 xofs3 xofs2 xofs1 xofs0 pixel number 91 xpix7 xpix6 xpix5 xpix4 xpix3 xpix2 xpix1 xpix0 vertical offset odd 92 yofso7 yofso6 yofso5 yofso4 yofso3 yofso2 yofso1 yofso0 vertical offset even 93 yofse7 yofse6 yofse5 yofse4 yofse3 yofse2 yofse1 yofse0 msbs 94 yofse9 yofse8 yofso9 yofso8 xpix9 xpix8 xofs9 xofs8 line number 95 ypix7 ypix6 ypix5 ypix4 ypix3 ypix2 ypix1 ypix0 scaler ctrl, mcb ypix 96 efs pcbn slave ilc yfil [1] ypix9 ypix8 sync control 97 hfs vfs ofs pfs ovs pvs ohs phs line length 98 hlen7 hlen6 hlen5 hlen4 hlen3 hlen2 hlen1 hlen0 input delay, msb line length 99 idel3 idel2 idel1 idel0 hlen11 hlen10 hlen9 hlen8 horizontal increment 9a xinc7 xinc6 xinc5 xinc4 xinc3 xinc2 xinc1 xinc0 vertical increment 9b yinc7 yinc6 yinc5 yinc4 yinc3 yinc2 yinc1 yinc0 msbs vertical and horizontal increment 9c yinc11 yinc10 yinc9 yinc8 xinc11 xinc10 xinc9 xinc8 weighting factor odd 9d yiwgto7 yiwgto6 yiwgto5 yiwgto4 yiwgto3 yiwgto2 yiwgto1 yiwgto0 table 48. slave receiver bit allocation map (slave address 88h) continued register function subaddress (hexadecimal) d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 102 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec weighting factor even 9e yiwgte7 yiwgte6 yiwgte5 yiwgte4 yiwgte3 yiwgte2 yiwgte1 yiwgte0 weighting factor msb 9f yiwgte11 yiwgte10 yiwgte9 yiwgte8 yiwgto11 yiwgto10 yiwgto9 yiwgto8 vertical line skip a0 yskip7 yskip6 yskip5 yskip4 yskip3 yskip2 yskip1 yskip0 blank enable for ni-bypass, vertical line skip msb a1 blen [1] [1] [1] yskip11 yskip10 yskip9 yskip8 border color y a2 bcy7 bcy6 bcy5 bcy4 bcy3 bcy2 bcy1 bcy0 border color u a3 bcu7 bcu6 bcu5 bcu4 bcu3 bcu2 bcu1 bcu0 border color v a4 bcv7 bcv6 bcv5 bcv4 bcv3 bcv2 bcv1 bcv0 hd sync line count array d0 ram address (see t ab le 112 ) hd sync line type array d1 ram address (see t ab le 114 ) hd sync line pattern array d2 ram address (see t ab le 116 ) hd sync value array d3 ram address (see t ab le 118 ) hd sync trigger state 1 d4 hlct7 hlct6 hlct5 hlct4 hlct3 hlct2 hlct1 hlct0 hd sync trigger state 2 d5 hlcpt3 hlcpt2 hlcpt1 hlcpt0 hlppt1 hlppt0 hlct9 hlct8 hd sync trigger state 3 d6 hdct7 hdct6 hdct5 hdct4 hdct3 hdct2 hdct1 hdct0 hd sync trigger state 4 d7 [1] hept2 hept1 hept0 [1] [1] hdct9 hdct8 hd sync trigger phase x d8 htx7 htx6 htx5 htx4 htx3 htx2 htx1 htx0 d9 [1] [1] [1] [1] htx11 htx10 htx9 htx8 hd sync trigger phase y da hty7 hty6 hty5 hty4 hty3 hty2 hty1 hty0 db [1] [1] [1] [1] [1] [1] hty9 hty8 hd output control dc [1] [1] [1] [1] hdsye hdtc hdgy hdip cursor color 1 r f0 cc1r7 cc1r6 cc1r5 cc1r4 cc1r3 cc1r2 cc1r1 cc1r0 cursor color 1 g f1 cc1g7 cc1g6 cc1g5 cc1g4 cc1g3 cc1g2 cc1g1 cc1g0 cursor color 1 b f2 cc1b7 cc1b6 cc1b5 cc1b4 cc1b3 cc1b2 cc1b1 cc1b0 cursor color 2 r f3 cc2r7 cc2r6 cc2r5 cc2r4 cc2r3 cc2r2 cc2r1 cc2r0 cursor color 2 g f4 cc2g7 cc2g6 cc2g5 cc2g4 cc2g3 cc2g2 cc2g1 cc2g0 cursor color 2 b f5 cc2b7 cc2b6 cc2b5 cc2b4 cc2b3 cc2b2 cc2b1 cc2b0 auxiliary cursor color r f6 auxr7 auxr6 auxr5 auxr4 auxr3 auxr2 auxr1 auxr0 auxiliary cursor color g f7 auxg7 auxg6 auxg5 auxg4 auxg3 auxg2 auxg1 auxg0 auxiliary cursor color b f8 auxb7 auxb6 auxb5 auxb4 auxb3 auxb2 auxb1 auxb0 table 48. slave receiver bit allocation map (slave address 88h) continued register function subaddress (hexadecimal) d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 103 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] all unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. horizontal cursor position f9 xcp7 xcp6 xcp5 xcp4 xcp3 xcp2 xcp1 xcp0 horizontal hot spot, msb xcp fa xhs4 xhs3 xhs2 xhs1 xhs0 xcp10 xcp9 xcp8 vertical cursor position fb ycp7 ycp6 ycp5 ycp4 ycp3 ycp2 ycp1 ycp0 vertical hot spot, msb ycp fc yhs4 yhs3 yhs2 yhs1 yhs0 [1] ycp9 ycp8 input path control fd lutoff cmode lutl if2 if1 if0 matoff dfoff cursor bit map fe ram address (see t ab le 133 ) color look-up table ff ram address (see t ab le 134 ) table 48. slave receiver bit allocation map (slave address 88h) continued register function subaddress (hexadecimal) d7 d6 d5 d4 d3 d2 d1 d0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 104 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.1.1 i 2 c-bus format a. to control registers b. to the hd line count array (subaddress d0h) c. to cursor bit map (subaddress feh) d. to color look-up table (subaddress ffh) see t ab le 49 for explanations. fig 50. i 2 c-bus write access a. to control registers b. to cursor bit map or color lut see t ab le 49 for explanations. fig 51. i 2 c-bus read access 001aad411 1000 1000 subaddress data 0 data n ............ s a a a ap 001aad412 1000 1000 ram address data 00 data 01 data n ............ s a d0h a a a a ap 001aad413 1000 1000 ram address data 0 data n ............ s a feh a a a ap 001aad414 1000 1000 ram address data 0r data 0g data 0b ............ s a ffh a a a a ap 001aad415 1000 1000 1000 1001 subaddress data 0 data n ............ s a a sr a am am p 001aad416 1000 1000 1000 1001 ram address data 0 data n .......... s a feh or ffh a a sr a am am p
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 105 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read. [2] if more than 1 byte of data is transmitted, then auto-increment of the subaddress is performed. 11.1.2 slave receiver table 49. explanations of figure 50 and figure 51 code description s start condition sr repeated start condition 1000 100x [1] slave address a acknowledge generated by the slave am acknowledge generated by the master subaddress [2] subaddress byte data data byte -------- continued data bytes and acknowledges p stop condition ram address start address for ram access table 50. common dac adjust ?ne register, subaddress 16h, bit description legend: * = default value after reset. bit symbol access value description 7 to 4 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 dacf[3:0] r/w dac ?ne output voltage adjustment, 1 % steps for all dacs 0111 7 % 0110 6 % 0101 5 % 0100 4 % 0011 3 % 0010 2 % 0001 1 % 0000* 0 % 1000 0 % 1001 - 1% 1010 - 2% 1011 - 3% 1100 - 4% 1101 - 5% 1110 - 6% 1111 - 7%
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 106 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 51. rgb dac adjust coarse registers, subaddresses 17h to 19h, bit description subaddress bit symbol description 17h to 19h 7 to 5 - must be programmed with logic 0 to ensure compatibility to future enhancements 17h 4 to 0 rdacc[4:0] output level coarse adjustment for red dac; default after reset is 1bh for output of c signal 0 0000b o 0.585 v to 1 1111b o 1.240 v at 37.5 w nominal for full-scale conversion 18h 4 to 0 gdacc[4:0] output level coarse adjustment for green dac; default after reset is 1bh for output of vbs signal 0 0000b o 0.585 v to 1 1111b o 1.240 v at 37.5 w nominal for full-scale conversion 19h 4 to 0 bdacc[4:0] output level coarse adjustment for blue dac; default after reset is 1fh for output of cvbs signal 0 0000b o 0.585 v to 1 1111b o 1.240 v at 37.5 w nominal for full-scale conversion table 52. msm threshold, subaddress 1ah, bit description bit symbol description 7 to 0 msmt[7:0] monitor sense mode threshold for dac output voltage, should be set to 70h table 53. monitor sense mode register, subaddress 1bh, bit description legend: * = default value after reset. bit symbol access value description 7 msm r/w monitor sense mode 0* off; rcomp, gcomp and bcomp bits are not valid 1on 6 msa r/w automatic monitor sense mode 0* off; rcomp, gcomp and bcomp bits are not valid 1 on if msm = 0 5 msoe r/w 0 pin tvd is active 1* pin tvd is 3-state 4 and 3 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 2 rcomp r check comparator at dac on pin red_cr_c_cvbs 0 active, output is loaded 1 inactive, output is not loaded 1 gcomp r check comparator at dac on pin green_vbs_cvbs 0 active, output is loaded 1 inactive, output is not loaded 0 bcomp r check comparator at dac on pin blue_cb_cvbs 0 active, output is loaded 1 inactive, output is not loaded
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 107 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 54. wide screen signal registers, subaddresses 26h and 27h, bit description legend: * = default value after reset. subaddress bit symbol access value description 27h 7 wsson r/w 0* wide screen signalling output is disabled 1 wide screen signalling output is enabled 6 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 5 to 3 wss[13:11] r/w - wide screen signalling bits, reserved 2 to 0 wss[10:8] r/w - wide screen signalling bits, subtitles 26h 7 to 4 wss[7:4] r/w - wide screen signalling bits, enhanced services 3 to 0 wss[3:0] r/w - wide screen signalling bits, aspect ratio table 55. real-time control and burst start register, subaddress 28h, bit description legend: * = default value after reset. bit symbol access value description 7 and 6 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 5 to 0 bs[5:0] r/w starting point of burst in clock cycles 21h* pal: bs = 33; strapping pin fsvgc tied to high 19h* ntsc: bs = 25; strapping pin fsvgc tied to low table 56. sync reset enable and burst end register, subaddress 29h, bit description legend: * = default value after reset. bit symbol access value description 7 sres r/w 0* pin ttx_sres accepts a teletext bit stream (ttx) 1 pin ttx_sres accepts a sync reset input (sres); a high impulse resets synchronization of the encoder (?rst ?eld, ?rst line) 6 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 5 to 0 be[5:0] r/w ending point of burst in clock cycles 1dh* pal: be = 29; strapping pin fsvgc tied to high 1dh* ntsc: be = 29; strapping pin fsvgc tied to low
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 108 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 57. copy generation 0, 1, 2 and cg enable registers, subaddresses 2ah to 2ch, bit description legend: * = default value after reset. subaddress bit symbol access value description 2ch 7 cgen r/w copy generation data output 0* disabled 1 enabled 6 to 4 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 cg[19:16] r/w - lsbs of the respective bytes are encoded immediately after run-in, the msbs of the respective bytes have to carry the crcc bits, in accordance with the de?nition of copy generation management system encoding format. 2bh 7 to 0 cg[15:8] 2ah 7 to 0 cg[7:0] table 58. output port control register, subaddress 2dh, bit description legend: * = default value after reset. bit symbol access value description 7 vbsen r/w pin green_vbs_cvbs provides a 0 component green signal (cvbsen1 = 0) or cvbs signal (cvbsen1 = 1) 1* luminance (vbs) signal 6 cvbsen1 r/w pin green_vbs_cvbs provides a 0* component green (g) or luminance (vbs) signal 1 cvbs signal 5 cvbsen0 r/w pin blue_cb_cvbs provides a 0 component blue (b) or color difference blue (c b ) signal 1* cvbs signal 4 cen r/w pin red_cr_c_cvbs provides a 0 component red (r) or color difference red (c r ) signal 1* chrominance signal (c) as modulated subcarrier for s-video 3 encoff r/w encoder 0* active 1 bypass, dacs are provided with rgb signal after cursor insertion block 2 clk2en r/w pin ttxrq_xclko2 provides 0 teletext request signal (ttxrq) 1* buffered crystal clock divided by two (13.5 mhz) 1 cvbsen2 r/w pin red_cr_c_cvbs provides a 0* signal according to cen 1 cvbs signal 0 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 109 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 59. input path control register, subaddress 37h, bit description legend: * = default value after reset. bit symbol access value description 7 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 6 yupsc r/w vertical scaler 0* normal operation 1 upscaling is enabled 5 and 4 yfil[1:0] r/w vertical interpolation ?lter control; the ?lter is not available if yupsc = 1 00* no ?lter active 01 ?lter is inserted before vertical scaling 10 ?lter is inserted after vertical scaling; yskip should be logic 0 11 reserved 3 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 2 czoom r/w cursor generator 0* normal operation 1 cursor will be zoomed by a factor of 2 in both directions 1 igain r/w expected input level swing is 0* 16 to 235 (8-bit rgb) 1 0 to 255 (8-bit rgb) 0 xint r/w interpolation ?lter for horizontal upscaling 0* not active 1 active table 60. gain luminance for rgb register, subaddress 38h, bit description legend: * = default value after reset. bit symbol access value description 7 to 5 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 4 to 0 gy[4:0] r/w - gain luminance of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = 0, depending on external application. table 61. gain color difference for rgb register, subaddress 39h, bit description legend: * = default value after reset. bit symbol access value description 7 to 5 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 4 to 0 gcd[4:0] r/w - gain color difference of rgb (c r , y and c b ) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = 0, depending on external application.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 110 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 62. input port control 1 register, subaddress 3ah, bit description legend: * = default value after reset. bit symbol access value description 7 cbenb r/w 0 data from input ports is encoded 1 color bar with ?xed colors is encoded 6 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 5 syntv r/w in slave mode 0* the encoder is only synchronized at the beginning of an odd ?eld 1 the encoder receives a vertical sync signal 4 symp r/w horizontal and vertical trigger 0* taken from fsvgc or both vsvgc and hsvgc 1 decoded out of itu-r bt.656 compatible data at pd port 3 demoff r/w y-c b -c r to rgb dematrix 0* active 1 bypassed 2 csync r/w pin hsm_csync provides 0 horizontal sync for non-interlaced vga components output (at pixclk) 1 composite sync for interlaced components output (at xtal clock) 1 y2c r/w input luminance data 0 twos complement from pd input port 1* straight binary from pd input port 0 uv2c r/w input color difference data 0 twos complement from pd input port 1* straight binary from pd input port table 63. vps enable, input control 2, subaddress 54h, bit description legend: * = default value after reset. bit symbol access value description 7 vpsen r/w video programming system data insertion 0* is disabled 1 in line 16 is enabled 6 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 5 gpval r/w if gpen = 1, pin vsm provides 0 low level 1 high level 4 gpen r/w pin vsm provides 0* vertical sync for a monitor 1 constant signal according to gpval 3 and 2 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 111 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] in line 16; lsb ?rst; all other bytes are not relevant for vps. 1 edge r/w input data is sampled with 0 inverse clock edges 1* the clock edges speci?ed in t ab le 12 to t ab le 18 0 slot r/w 0* normal assignment of the input data to the clock edge 1 correct time misalignment due to inverted assignment of input data to the clock edge table 64. vps byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit description [1] subaddress bit symbol access value description 55h 7 to 0 vps5[7:0] r/w - ?fth byte of video programming system data 56h 7 to 0 vps11[7:0] r/w - eleventh byte of video programming system data 57h 7 to 0 vps12[7:0] r/w - twelfth byte of video programming system data 58h 7 to 0 vps13[7:0] r/w - thirteenth byte of video programming system data 59h 7 to 0 vps14[7:0] r/w - fourteenth byte of video programming system data table 65. chrominance phase register, subaddress 5ah, bit description legend: * = default value after reset. bit symbol access value description 7 to 0 chps[7:0] r/w 00h* phase of encoded color subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 6bh pal b/g and data from input ports in master mode 16h pal b/g and data from look-up table 25h ntsc m and data from input ports in master mode 46h ntsc m and data from look-up table table 63. vps enable, input control 2, subaddress 54h, bit description continued legend: * = default value after reset. bit symbol access value description
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 112 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] variable gain for c b signal; input representation in accordance with itu-r bt.601 . [2] variable black level; input representation in accordance with itu-r bt.601 . [3] output black level/ire = blckl 2/6.29 + 28.9. [4] output black level/ire = blckl 2/6.18 + 26.5. [1] variable gain for c r signal; input representation in accordance with itu-r bt.601 . [2] variable blanking level. [3] output black level/ire = blnnl 2/6.29 + 25.4. [4] output black level/ire = blnnl 2/6.18 + 25.9; default after reset: 35h. table 66. gain u and gain u msb, black level registers, subaddresses 5bh and 5dh, bit description subaddress bit symbol conditions remarks 5bh 7 to 0 gainu[8:0] [1] white-to-black = 92.5 ire gainu = - 2.17 nominal to +2.16 nominal 5dh 7 gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire gainu = - 2.05 nominal to +2.04 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal 6 - must be programmed with logic 0 to ensure compatibility to future enhancements 5 to 0 blckl[5:0] [2] white-to-sync = 140 ire [3] recommended value: blckl = 58 (3ah) blckl = 0 [3] output black level = 29 ire blckl = 63 (3fh) [3] output black level = 49 ire white-to-sync = 143 ire [4] recommended value: blckl = 51 (33h) blckl = 0 [4] output black level = 27 ire blckl = 63 (3fh) [4] output black level = 47 ire table 67. gain v and gain v msb, blanking level registers, subaddresses 5ch and 5eh, bit description subaddress bit symbol conditions remarks 5ch 7 to 0 gainv[8:0] [1] white-to-black = 92.5 ire gainv = - 1.55 nominal to +1.55 nominal 5eh 7 gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire gainv = - 1.46 nominal to +1.46 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal 6 - must be programmed with logic 0 to ensure compatibility to future enhancements 5 to 0 blnnl[5:0] [2] white-to-sync = 140 ire [3] recommended value: blnnl = 46 (2eh) blnnl = 0 [3] output blanking level = 25 ire blnnl = 63 (3fh) [3] output blanking level = 45 ire white-to-sync = 143 ire [4] recommended value: blnnl = 53 (35h) blnnl = 0 [4] output blanking level = 26 ire blnnl = 63 (3fh) [4] output blanking level = 46 ire
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 113 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 68. ccr and blanking level vbi register, subaddress 5fh, bit description bit symbol access value description 7 and 6 ccrs[1:0] r/w select cross-color reduction ?lter in luminance; for overall transfer characteristic of luminance see figure 9 00 no cross-color reduction 01 cross-color reduction #1 active 10 cross-color reduction #2 active 11 cross-color reduction #3 active 5 to 0 blnvb[5:0] r/w - variable blanking level during vertical blanking interval is typically identical to value of blnnl table 69. standard control register, subaddress 61h, bit description legend: * = default value after reset. bit symbol access value description 7 downd r/w digital core 0* in normal operational mode 1 in sleep mode and is reactivated with an i 2 c-bus address 6 downa r/w dacs 0* in normal operational mode 1 in power-down mode 5 inpi r/w pal switch 0* phase is nominal 1 is inverted compared to nominal if rtce = 1 4 ygs r/w luminance gain for white - black 0 100 ire 1 92.5 ire including 7.5 ire set-up of black 3 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 2 scbw r/w bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figure 7 and figure 8 ) 0 enlarged 1* standard 1 pal r/w encoding 0 ntsc (non-alternating v component) 1 pal (alternating v component) 0 fise r/w total pixel clocks per line 0 864 1 858
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 114 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] examples: a) ntsc m: f fsc = 227.5, f llc = 1716 ? fsc = 569408543 (21f0 7c1fh). b) pal b/g: f fsc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a09 8acbh). [1] lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format. table 70. burst amplitude register, subaddress 62h, bit description legend: * = default value after reset, ^ = recommended value. bit symbol access value description 7 rtce r/w real-time control 0* no real-time control of generated subcarrier frequency 1 real-time control of generated subcarrier frequency through a nxp video decoder; for a speci?cation of the rtc protocol see document how to use real time control (rtc) , available on request 6 to 0 bsta[6:0] r/w amplitude of color burst; input representation in accordance with itu-r bt.601 3fh (63)^ white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding; bsta = 0 to 2.02 nominal 2dh (45)^ white-to-black = 92.5 ire; burst = 40 ire; pal encoding; bsta = 0 to 2.82 nominal 43h (67)^ white-to-black = 100 ire; burst = 43 ire; ntsc encoding; bsta = 0 to 1.90 nominal 2fh (47)*^ white-to-black = 100 ire; burst = 43 ire; pal encoding; bsta = 0 to 3.02 nominal table 71. subcarrier 0, 1, 2 and 3 registers, subaddresses 63h to 66h, bit description subaddress bit symbol access value description 66h 7 to 0 fsc[31:24] r/w - f fsc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency); fsc[31:24] = most signi?cant byte; fsc[07:00] = least signi?cant byte [1] 65h 7 to 0 fsc[23:16] r/w - 64h 7 to 0 fsc[15:08] r/w - 63h 7 to 0 fsc[07:00] r/w - table 72. line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6ah, bit description [1] subaddress bit symbol access value description 67h 7 to 0 l21o[07:00] r/w - ?rst byte of captioning data, odd ?eld 68h 7 to 0 l21o[17:10] r/w - second byte of captioning data, odd ?eld 69h 7 to 0 l21e[07:00] r/w - ?rst byte of extended data, even ?eld 6ah 7 to 0 l21e[17:10] r/w - second byte of extended data, even ?eld fsc round f fsc f llc --------- - 2 32 ? ?? =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 115 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed; increasing htrig decreases delays of all internally generated timing signals. [2] increasing vtrig decreases delays of all internally generated timing signals, measured in half lines; variation range of vtri g=0to31 (1fh). table 73. trigger control registers, subaddresses 6ch and 6dh, bit description legend: * = default value after reset. subaddress bit symbol access value description 6ch 7 to 0 htrig[7:0] r/w 00h* sets the horizontal trigger phase related to chip-internal horizontal input [1] 6dh 7 to 5 htrig[10:8] r/w 0h* 4 to 0 vtrig[4:0] r/w 00h* sets the vertical trigger phase related to chip-internal vertical input [2] table 74. multi control register, subaddress 6eh, bit description legend: * = default value after reset. bit symbol access value description 7 nvtrig r/w values of the vtrig register are 0 positive 1 negative 6 blckon r/w 0* encoder in normal operation mode 1 output signal is forced to blanking level 5 and 4 phres[1:0] r/w selects the phase reset mode of the color subcarrier generator 00 no subcarrier reset 01 subcarrier reset every two lines 10 subcarrier reset every eight ?elds 11 subcarrier reset every four ?elds 3 and 2 ldel[1:0] r/w selects the delay on luminance path with reference to chrominance path 00* no luminance delay 01 1 llc luminance delay 10 2 llc luminance delay 11 3 llc luminance delay 1 and 0 flc[1:0] r/w ?eld length control 00* interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz 01 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 10 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 11 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 116 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed. table 75. closed caption, teletext enable register, subaddress 6fh, bit description legend: * = default value after reset. bit symbol access value description 7 and 6 ccen[1:0] r/w enables individual line 21 encoding 00* line 21 encoding off 01 enables encoding in ?eld 1 (odd) 10 enables encoding in ?eld 2 (even) 11 enables encoding in both ?elds 5 ttxen r/w teletext insertion 0* disabled 1 enabled 4 to 0 sccln[4:0] r/w - selects the actual line, where closed caption or extended data are encoded; line = (sccln + 4) for m-systems; line = (sccln + 1) for other systems table 76. active display window horizontal (adwh) start and end registers, subaddresses 70h to 72h, bit description subaddress bit symbol access value description 70h 7 to 0 adwhs[7:0] r/w - active display window horizontal start; de?nes the start of the active tv display portion after the border color [1] 71h 7 to 0 adwhe[7:0] r/w - active display window horizontal end; de?nes the end of the active tv display portion before the border color [1] 72h 7 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 6 to 4 adwhe[10:8] r/w - active display window horizontal end; de?nes the end of the active tv display portion before the border color [1] 3 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 2 to 0 adwhs[10:8] r/w - active display window horizontal start; de?nes the start of the active tv display portion after the border color [1] table 77. ttx request horizontal start register, subaddress 73h, bit description legend: * = default value after reset. bit symbol access value description 7 to 0 ttxhs[7:0] r/w start of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0); see figure 66 42h* if strapped to pal 54h* if strapped to ntsc
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 117 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 78. ttx request horizontal delay register, subaddress 74h, bit description legend: * = default value after reset and minimum value. bit symbol access value description 7 to 4 - r/w 0h must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 ttxhd[3:0] r/w 2h* indicates the delay in clock cycles between rising edge of ttxrq output signal on pin ttxrq_xclko2 (clk2en = 0) and valid data at pin ttx_sres table 79. csync advance register, subaddress 75h, bit description bit symbol access value description 7 to 3 csynca[4:0] r/w - advanced composite sync against rgb output from 0 xtal clocks to 31 xtal clocks 2 to 0 - r/w 000 must be programmed with logic 0 to ensure compatibility to future enhancements table 80. ttx odd request vertical start register, subaddress 76h, bit description legend: * = default value after reset. bit symbol access value description 7 to 0 ttxovs[7:0] r/w with ttxovs8 (see t ab le 86 ) ?rst line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in odd ?eld, line = (ttxovs + 4) for m-systems and line = (ttxovs + 1) for other systems 05h* if strapped to pal 06h* if strapped to ntsc table 81. ttx odd request vertical end register, subaddress 77h, bit description legend: * = default value after reset. bit symbol access value description 7 to 0 ttxove[7:0] r/w with ttxove8 (see t ab le 86 ) last line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in odd ?eld, line = (ttxove + 3) for m-systems and line = ttxove for other systems 16h* if strapped to pal 10h* if strapped to ntsc table 82. ttx even request vertical start register, subaddress 78h, bit description legend: * = default value after reset. bit symbol access value description 7 to 0 ttxevs[7:0] r/w with ttxevs8 (see t ab le 86 ) ?rst line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in even ?eld, line = (ttxevs + 4) for m-systems and line = (ttxevs + 1) for other systems 04h* if strapped to pal 05h* if strapped to ntsc
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 118 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 83. ttx even request vertical end register, subaddress 79h, bit description legend: * = default value after reset. bit symbol access value description 7 to 0 ttxeve[7:0] r/w with ttxeve8 (see t ab le 86 ) last line of occurrence of signal ttxrq on pin ttxrq_xclko2 (clk2en = 0) in even ?eld, line = (ttxeve + 3) for m-systems and line = ttxeve for other systems 16h* if strapped to pal 10h* if strapped to ntsc table 84. first active line register, subaddress 7ah, bit description bit symbol access value description 7 to 0 fal[7:0] r/w with fal8 (see t ab le 86 ) ?rst active line = (fal + 4) for m-systems and (fal + 1) for other systems, measured in lines 00h coincides with the ?rst ?eld synchronization pulse table 85. last active line register, subaddress 7bh, bit description bit symbol access value description 7 to 0 lal[7:0] r/w with lal8 (see t ab le 86 ) last active line = (lal + 3) for m-systems and lal for other system, measured in lines 00h coincides with the ?rst ?eld synchronization pulse table 86. ttx mode, msb vertical register, subaddress 7ch, bit description legend: * = default value after reset. bit symbol access value description 7 ttx60 r/w 0* enables nabts (fise = 1) or european ttx (fise = 0) 1 enables world standard teletext 60 hz (fise = 1) 6 lal8 r/w see t ab le 85 5 ttxo r/w teletext protocol selected (see figure 66 ) 0* new teletext protocol selected; at each rising edge of ttxrq a single teletext bit is requested 1 old teletext protocol selected; the encoder provides a window of ttxrq going high; the length of the window depends on the chosen teletext standard 4 fal8 r/w see t ab le 84 3 ttxeve8 r/w see t ab le 83 2 ttxove8 r/w see t ab le 81 1 ttxevs8 r/w see t ab le 82 0 ttxovs8 r/w see t ab le 80
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 119 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] this bit mask is effective only if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve. table 87. disable ttx line registers, subaddresses 7eh and 7fh, bit description [1] subaddress bit symbol access value description 7eh 7 to 0 line[12:5] r/w - individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective bits, disabled line = linexx (50 hz ?eld rate) 7fh 7 to 0 line[20:13] r/w - table 88. pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description subaddress bit symbol access value description 81h 7 to 0 pcl[07:00] r/w de?nes the frequency of the synthesized pixel clock pixclko; ; f xtal = 27 mhz nominal 82h 7 to 0 pcl[15:08] 83h 7 to 0 pcl[23:16] 20 f63bh 640 480 to ntsc m 1b 5a73h 640 480 to pal b/g (as by strapping pins) table 89. pixel clock control register, subaddress 84h, bit description legend: * = default value after reset. bit symbol access value description 7 dclk r/w 0* set to logic 1 1 set to logic 1 6 pclsy r/w pixel clock generator 0* runs free 1 gets synchronized with the vertical sync 5 ifra r/w input fifo gets reset 0 explicitly at falling edge 1* every ?eld 4 ifbp r/w input fifo 0 active 1* bypassed 3 and 2 pcle[1:0] r/w controls the divider for the external pixel clock 00 divider ratio for pixclk output is 1 01* divider ratio for pixclk output is 2 10 divider ratio for pixclk output is 4 11 divider ratio for pixclk output is 8 1 and 0 pcli[1:0] r/w controls the divider for the internal pixel clock 00 divider ratio for internal pixclk is 1 01* divider ratio for internal pixclk is 2 10 divider ratio for internal pixclk is 4 11 not allowed f pixclk pcl 2 24 ----------- f xtal ? ?? 8 =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 120 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 90. fifo control register, subaddress 85h, bit description legend: * = default value after reset, ^ = nominal value. bit symbol access value description 7 eidiv r/w 0* dvo compliant signals are applied 1 non-dvo compliant signals are applied 6 to 4 - r/w 000 must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 fili[3:0] r/w 8h*^ threshold for fifo internal transfers table 91. horizontal offset register, subaddress 90h, bit description bit symbol description 7 to 0 xofs[7:0] with xofs[9:8] (see t ab le 95 ) horizontal offset; de?nes the number of pixclks from horizontal sync (hsvgc) output to composite blanking ( cbo) output table 92. pixel number register, subaddress 91h, bit description bit symbol description 7 to 0 xpix[7:0] with xpix[9:8] (see t ab le 95 ) pixel in x direction; de?nes half the number of active pixels per input line (identical to the length of cbo pulses) table 93. vertical offset odd register, subaddress 92h, bit description bit symbol description 7 to 0 yofso[7:0] with yofso[9:8] (see t ab le 95 ) vertical offset in odd ?eld; de?nes (in the odd ?eld) the number of lines from vsvgc to ?rst line with active cbo; if no lut data is requested, the ?rst active cbo will be output at yofso + 2; usually, yofso = yofse with the exception of extreme vertical downscaling and interlacing table 94. vertical offset even register, subaddress 93h, bit description bit symbol description 7 to 0 yofse[7:0] with yofse[9:8] (see t ab le 95 ) vertical offset in even ?eld; de?nes (in the even ?eld) the number of lines from vsvgc to ?rst line with active cbo; if no lut data is requested, the ?rst active cbo will be output at yofse + 2; usually, yofse = yofso with the exception of extreme vertical downscaling and interlacing table 95. msbs register, subaddress 94h, bit description bit symbol description 7 and 6 yofse[9:8] see t ab le 94 5 and 4 yofso[9:8] see t ab le 93 3 and 2 xpix[9:8] see t ab le 92 1 and 0 xofs[9:8] see t ab le 91 table 96. line number register, subaddress 95h, bit description bit symbol description 7 to 0 ypix[7:0] with ypix[9:8] (see t ab le 97 ) de?nes the number of requested input lines from the feeding device; number of requested lines = ypix + yofse - yofso
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 121 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 97. scaler ctrl, mcb and ypix register, subaddress 96h, bit description bit symbol access value description 7 efs r/w in slave mode frame sync signal at pin fsvgc 0 ignored 1 accepted 6 pcbn r/w polarity of cbo signal 0 normal (high during active video) 1 inverted (low during active video) 5 slave r/w from the saa7104e; saa7105e the timing to the graphics controller is 0 master 1 slave 4 ilc r/w if hardware cursor insertion is active 0 set low for non-interlaced input signals 1 set high for interlaced input signals 3 yfil r/w luminance sharpness booster 0 disabled 1 enabled 2 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 1 and 0 ypix[9:8] see t ab le 96 table 98. sync control register, subaddress 97h, bit description bit symbol access value description 7 hfs r/w horizontal sync is derived from 0 input signal (save mode) at pin hsvgc 1 a frame sync signal (slave mode) at pin fsvgc (only if efs is set high) 6 vfs r/w vertical sync (?eld sync) is derived from 0 input signal (slave mode) at pin vsvgc 1 a frame sync signal (slave mode) at pin fsvgc (only if efs is set high) 5 ofs r/w pin fsvgc is 0 input 1 active output 4 pfs r/w polarity of signal at pin fsvgc in output mode (master mode) is 0 active high; rising edge of the input signal is used in slave mode 1 active low; falling edge of the input signal is used in slave mode 3 ovs r/w pin vsvgc is 0 input 1 active output
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 122 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 2 pvs r/w polarity of signal at pin vsvgc in output mode (master mode) is 0 active high; rising edge of the input signal is used in slave mode 1 active low; falling edge of the input signal is used in slave mode 1 ohs r/w pin hsvgc is 0 input 1 active output 0 phs r/w polarity of signal at pin hsvgc in output mode (master mode) is 0 active high; rising edge of the input signal is used in slave mode 1 active low; falling edge of the input signal is used in slave mode table 99. line length register, subaddress 98h, bit description bit symbol description 7 to 0 hlen[7:0] with hlen[11:8] (see t ab le 100 ) horizontal length; table 100. input delay, msb line length register, subaddress 99h, bit description bit symbol description 7 to 4 idel[3:0] input delay; de?nes the distance in pixclks between the active edge of cbo and the ?rst received valid pixel 3 to 0 hlen[11:8] see t ab le 99 table 101. horizontal increment register, subaddress 9ah, bit description bit symbol description 7 to 0 xinc[7:0] with xinc[11:8] (see t ab le 103 ) incremental fraction of the horizontal scaling engine; table 102. vertical increment register, subaddress 9bh, bit description bit symbol description 7 to 0 yinc[7:0] with yinc[11:8] (see t ab le 103 ) incremental fraction of the vertical scaling engine; table 98. sync control register, subaddress 97h, bit description continued bit symbol access value description hlen number of pixclks line ------------------------------------------------ -1 C = xinc number of output pixels line -------------------------------------------------------- number of input pixels line ----------------------------------------------------- -------------------------------------------------------- - 4096 = yinc number of active output lines number of active input lines --------------------------------------------------------------------- - 4096 =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 123 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 103. msbs vertical and horizontal increment register, subaddress 9ch, bit description bit symbol description 7 to 4 yinc[11:8] see t ab le 102 3 to 0 xinc[11:8] see t ab le 101 table 104. weighting factor odd register, subaddress 9dh, bit description bit symbol description 7 to 0 yiwgto[7:0] with yiwgto[11:8] (see t ab le 106 ) weighting factor for the ?rst line of the odd ?eld; table 105. weighting factor even, subaddress 9eh, bit description bit symbol description 7 to 0 yiwgte[7:0] with yiwgte[11:8] (see t ab le 106 ) weighting factor for the ?rst line of the even ?eld; table 106. weighting factor msb register, subaddress 9fh, bit description bit symbol description 7 to 4 yiwgte[11:8] see t ab le 105 3 to 0 yiwgto[11:8] see t ab le 104 table 107. vertical line skip register, subaddress a0h, bit description bit symbol access value description 7 to 0 yskip[7:0] r/w with yskip[11:8] (see t ab le 108 ) vertical line skip; de?nes the effectiveness of the anti-?icker ?lter 000h most effective fffh anti-?icker ?lter switched off table 108. blank enable for ni-bypass, vertical line skip msb register, subaddress a1h, bit description legend: * = default value after reset. bit symbol access value description 7 blen r/w for non-interlaced graphics in bypass mode 0* no internal blanking 1 forced internal blanking 6 to 4 - r/w 000 must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 yskip[11:8] r/w see t ab le 107 table 109. border color y register, subaddress a2h, bit description bit symbol description 7 to 0 bcy[7:0] luminance portion of border color in underscan area yiwgto yinc 2 ------------ - 2048 + = yiwgte yinc yskip C 2 ---------------------------------- - =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 124 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 110. border color u register, subaddress a3h, bit description bit symbol description 7 to 0 bcu[7:0] color difference portion of border color in underscan area table 111. border color v register, subaddress a4h, bit description bit symbol description 7 to 0 bcv[7:0] color difference portion of border color in underscan area table 112. subaddress d0h data byte description hlca ram start address for the hd sync line count array; the byte following subaddress d0 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line count array entry consists of 2 bytes; see t ab le 113 . the array has 15 entries. hlc hd line counter. the system will repeat the pattern described in hlt hlc times and then start with the next entry in line count array. hlt hd line type pointer. if not 0, the value points into the line type array, index hlt - 1 with the description of the current line. 0 means the entry is not used. table 113. layout of the data bytes in the line count array byte description 0 hlc7 hlc6 hlc5 hlc4 hlc3 hlc2 hlc1 hlc0 1 hlt3 hlt2 hlt1 hlt0 0 0 hlc9 hlc8 table 114. subaddress d1h data byte description hlta ram start address for the hd sync line type array; the byte following subaddress d1 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line type array entry consists of 4 bytes; see t ab le 115 . the array has 15 entries. hlp hd line type; if not 0, the value points into the line pattern array. the index used is hlp - 1. it consists of value-duration pairs. each entry consists of 8 pointers, used from index 0 to 7. the value 0 means that the entry is not used. table 115. layout of the data bytes in the line type array byte description 0 0 hlp12 hlp11 hlp10 0 hlp02 hlp01 hlp00 1 0 hlp32 hlp31 hlp30 0 hlp22 hlp21 hlp20 2 0 hlp52 hlp51 hlp50 0 hlp42 hlp41 hlp40 3 0 hlp72 hlp71 hlp70 0 hlp62 hlp61 hlp60
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 125 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 116. subaddress d2h data byte description hlpa ram start address for the hd sync line pattern array; the byte following subaddress d2 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes; see t ab le 117 . the array has 7 entries. hpd hd pattern duration. the value de?nes the time in pixel clocks (hpd + 1) the corresponding value hpv is added to the hd output signal. if 0, this entry will be skipped. hpv hd pattern value pointer. this gives the index in the hd value array containing the level to be inserted into the hd output path. if the msb of hpv is logic 1, the value will only be inserted into the y/green channel of the hd data path, the other channels remain unchanged. table 117. layout of the data bytes in the line pattern array byte description 0 hpd07 hpd06 hpd05 hpd04 hpd03 hpd02 hpd01 hpd00 1 hpv03 hpv02 hpv01 hpv00 0 0 hpd09 hpd08 2 hpd17 hpd16 hpd14 hpd14 hpd13 hpd12 hpd11 hpd10 3 hpv13 hpv12 hpv11 hpv10 0 0 hpd19 hpd18 4 hpd27 hpd26 hpd25 hpd24 hpd23 hpd22 hpd21 hpd20 5 hpv23 hpv22 hpv21 hpv20 0 0 hpd29 hpd28 6 hpd37 hpd36 hpd35 hpd34 hpd33 hpd32 hpd31 hpd30 7 hpv33 hpv32 hpv31 hpv30 0 0 hpd39 hpd38 table 118. subaddress d3h data byte description hpva ram start address for the hd sync value array; the byte following subaddress d3 points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. each line pattern array entry consists of 2 bytes. the array has 8 entries. hpve hd pattern value entry. the hd path will insert a level of (hpv + 52) 0.66 ire into the data path. the value is signed 8-bits wide; see t ab le 119 . hhs hd horizontal sync. if the hd engine is active, this value will be provided at pin hsm_csync; see t ab le 119 . hvs hd vertical sync. if the hd engine is active, this value will be provided at pin vsm; see t ab le 119 . table 119. layout of the data bytes in the value array byte description 0 hpve7 hpve6 hpve5 hpve4 hpve3 hpve2 hpve1 hpve0 1 000000hvshhs table 120. hd sync trigger state 1 register, subaddress d4h, bit description bit symbol description 7 to 0 hlct[7:0] with hlct[9:8] (see t ab le 121 ) state of the hd line counter after trigger (counts backwards)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 126 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 121. hd sync trigger state 2 register, subaddress d5h, bit description bit symbol description 7 to 4 hlcpt[3:0] state of the hd line type pointer after trigger 3 and 2 hlppt[1:0] state of the hd pattern pointer after trigger 1 and 0 hlct[9:8] see t ab le 120 table 122. hd sync trigger state 3 register, subaddress d6h, bit description bit symbol description 7 to 0 hdct[7:0] with hdct[9:8] (see t ab le 123 ) state of the hd duration counter after trigger (counts backwards) table 123. hd sync trigger state 4 register, subaddress d7h, bit description bit symbol description 7 - must be programmed with logic 0 to ensure compatibility to future enhancements 6 to 4 hept[2:0] state of the hd event type pointer in the line type array after trigger 3 and 2 - must be programmed with logic 0 to ensure compatibility to future enhancements 1 and 0 hdct[9:8] see t ab le 122 table 124. hd sync trigger phase x registers, subaddresses d8h and d9h, bit description subaddress bit symbol description d9h 7 to 4 - must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 htx[11:8] horizontal trigger phase for the hd sync engine in pixel clocks d8h 7 to 0 htx[7:0] table 125. hd sync trigger phase y registers, subaddresses dah and dbh, bit description subaddress bit symbol description dbh 7 to 2 - must be programmed with logic 0 to ensure compatibility to future enhancements 1 and 0 hty[9:8] vertical trigger phase for the hd sync engine in input lines dah 7 to 0 hty[7:0] table 126. hd output control register, subaddress dch, bit description legend: * = default value after reset. bit symbol access value description 7 to 4 - r/w 0 must be programmed with logic 0 to ensure compatibility to future enhancements 3 hdsye r/w hd sync engine 0* off 1 active 2 hdtc r/w hd output path processes 0* rgb 1 yuv
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 127 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 1 hdgy r/w 0* gain in the hd output path is reduced, insertion of sync pulses is possible 1 full level swing at the input causes full level swing at the dacs in hd mode 0 hdip r/w interpolator for the color difference signal in the hd output path 0* active 1 off table 127. cursor color 1 r, g and b registers, subaddresses f0h to f2h, bit description subaddress bit symbol description f0h 7 to 0 cc1r[7:0] red portion of ?rst cursor color f1h 7 to 0 cc1g[7:0] green portion of ?rst cursor color f2h 7 to 0 cc1b[7:0] blue portion of ?rst cursor color table 128. cursor color 2 r, g and b registers, subaddresses f3h to f5h, bit description subaddress bit symbol description f3h 7 to 0 cc2r[7:0] red portion of second cursor color f4h 7 to 0 cc2g[7:0] green portion of second cursor color f5h 7 to 0 cc2b[7:0] blue portion of second cursor color table 129. auxiliary cursor color r, g and b registers, subaddresses f6h to f8h, bit description subaddress bit symbol description f6h 7 to 0 auxr[7:0] red portion of auxiliary cursor color f7h 7 to 0 auxg[7:0] green portion of auxiliary cursor color f8h 7 to 0 auxb[7:0] blue portion of auxiliary cursor color table 130. horizontal cursor position and horizontal hot spot, msb xcp registers, subaddresses f9h and fah, bit description subaddress bit symbol description fah 7 to 3 xhs[4:0] horizontal hot spot of cursor 2 to 0 xcp[10:8] horizontal cursor position f9h 7 to 0 xcp[7:0] table 131. vertical cursor position and vertical hot spot, msb ycp registers, subaddresses fbh and fch, bit description subaddress bit symbol description fch 7 to 3 yhs[4:0] vertical hot spot of cursor 2 - must be programmed with logic 0 to ensure compatibility to future enhancements 1 and 0 ycp[9:8] vertical cursor position fbh 7 to 0 ycp[7:0] table 126. hd output control register, subaddress dch, bit description continued legend: * = default value after reset. bit symbol access value description
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 128 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec in subaddresses 5bh, 5ch, 5dh, 5eh, 62h and d3h all ire values are rounded up. table 132. input path control register, subaddress fdh, bit description bit symbol access value description 7 lutoff r/w color look-up table 0 active 1 bypassed 6 cmode r/w cursor mode 0 cursor mode; input color will be inverted 1 auxiliary cursor color will be inserted 5 lutl r/w lut loading via input data stream 0 inactive 1 color and cursor luts are loaded 4 to 2 if[2:0] r/w input format 000 8 + 8 + 8-bit 4:4:4 non-interlaced rgb or c b -y-c r 001 5 + 5 + 5-bit 4:4:4 non-interlaced rgb 010 5 + 6 + 5-bit 4:4:4 non-interlaced rgb 011 8 + 8 + 8-bit 4:2:2 non-interlaced c b -y-c r 100 8 + 8 + 8-bit 4:2:2 interlaced c b -y-c r (itu-r bt.656, 27 mhz clock) (in subaddresses 91h and 94h set xpix = number of active pixels/line) 101 8-bit non-interlaced index color 110 8 + 8 + 8-bit 4:4:4 non-interlaced rgb or c b -y-c r (special bit ordering) 1 matoff r/w rgb to c r -y-c b matrix 0 active 1 bypassed 0 dfoff r/w down formatter 0 (4:4:4to4:2:2) in input path is active 1 bypassed table 133. cursor bit map register, subaddress feh, bit description data byte description cursa ram start address for cursor bit map; the byte following subaddress feh points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition table 134. color look-up table register, subaddress ffh, bit description data byte description colsa ram start address for color lut; the byte following subaddress ffh points to the ?rst cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 129 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.1.3 slave transmitter table 135. status byte register, subaddress 00h, bit description bit symbol access value description 7 to 5 ver[2:0] r 101 version identi?cation of the device: it will be changed with all versions of the ic that have different programming models; current version is 101 binary 4 ccrdo r 1 set immediately after the closed caption bytes of the odd ?eld have been encoded 0 reset after information has been written to the subaddresses 67h and 68h 3 ccrde r 1 set immediately after the closed caption bytes of the even ?eld have been encoded 0 reset after information has been written to the subaddresses 69h and 6ah 2- r 0 - 1 fseq r 1 during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pal = 8 ?elds) 0 not ?rst ?eld of a sequence 0 o_e r 1 during even ?eld 0 during odd ?eld table 136. slave transmitter (slave address 89h) register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte 00h ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e chip id 1ch cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 fifo status 80h 0 0 0 0 0 0 ovfl udfl table 137. chip id register, subaddress 1ch, bit description bit symbol access value description 7 to 0 cid[7:0] r chip id 04h SAA7108AE 05h saa7109ae
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 130 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2 digital video decoder part 11.2.1 i 2 c-bus format table 138. fifo status register, subaddress 80h, bit description bit symbol access value description 7 to 4 - r 0h - 3 iferr r 0 normal fifo state 1 input fifo over?ow/under?ow has occurred 2 bferr r 0 normal fifo state 1 buffer fifo over?ow, only if yupsc = 1 1 ovfl r 0 no fifo over?ow 1 fifo over?ow has occurred; this bit is reset after this subaddress has been read 0 udfl r 0 no fifo under?ow 1 fifo under?ow has occurred; this bit is reset after this subaddress has been read a. write procedure. b. read procedure (combined). fig 52. i 2 c-bus format ack-s ack-s data slave address w data transferred (n bytes + acknowledge) mhb339 p s ack-s subaddress ack-s ack-m slave address r mhb340 p sr ack-s ack-s data subaddress slave address w s data transferred (n bytes + acknowledge)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 131 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] the SAA7108AE; saa7109ae supports the fast mode i 2 c-bus speci?cation extension (data rate up to 400 kbit/s). [2] if pin rtco is strapped to v ddd via a 3.3 k w resistor. table 139. description of i 2 c-bus format [1] code description s start condition sr repeated start condition slave address w 0100 0010 (42h, default) or 0100 0000 (40h) [2] slave address r 0100 0011 (43h, default) or 0100 0001 (41h) [2] ack-s acknowledge generated by the slave ack-m acknowledge generated by the master subaddress subaddress byte; see t ab le 140 and t ab le 141 data data byte; see t ab le 141 ; if more than one byte data is transmitted the subaddress pointer is automatically incremented p stop condition table 140. subaddress description and access subaddress description access (read/write) 00h chip version read only f0h to ffh reserved - video decoder: 01h to 2fh 01h to 05h front-end part read and write 06h to 19h decoder part read and write 1ah to 1eh reserved - 1fh video decoder status byte read only 20h to 2fh reserved - audio clock generation: 30h to 3fh 30h to 3ah audio clock generator read and write 3bh to 3fh reserved - general purpose vbi data slicer: 40h to 7fh 40h to 5eh vbi data slicer read and write 5fh reserved - 60h to 62h vbi data slicer status read only 63h to 7fh reserved - x port, i port and the scaler: 80h to efh 80h to 8fh task independent global settings read and write 90h to bfh task a de?nition read and write c0h to efh task b de?nition read and write
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 132 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 141. i 2 c-bus receiver/transmitter overview register function subaddress d7 d6 d5 d4 d3 d2 d1 d0 chip version: register 00h chip version (read only) 00h id7 id6 id5 id4 - - - - video decoder: registers 01h to 2fh front-end part: registers 01h to 05h increment delay 01h [1] [1] [1] [1] idel3 idel2 idel1 idel0 analog input control 1 02h fuse1 fuse0 gudl1 gudl0 mode3 mode2 mode1 mode0 analog input control 2 03h [1] hlnrs vbsl wpoff holdg gafix gai28 gai18 analog input control 3 04h gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 analog input control 4 05h gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 decoder part: registers 06h to 2fh horizontal sync start 06h hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 horizontal sync stop 07h hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 sync control 08h aufd fsel foet htc1 htc0 hpll vnoi1 vnoi0 luminance control 09h byps ycomb ldel lubw lufi3 lufi2 lufi1 lufi0 luminance brightness control 0ah dbri7 dbri6 dbri5 dbri4 dbri3 dbri2 dbri1 dbri0 luminance contrast control 0bh dcon7 dcon6 dcon5 dcon4 dcon3 dcon2 dcon1 dcon0 chrominance saturation control 0ch dsat7 dsat6 dsat5 dsat4 dsat3 dsat2 dsat1 dsat0 chrominance hue control 0dh huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 chrominance control 1 0eh cdto cstd2 cstd1 cstd0 dcvf fctc [1] ccomb chrominance gain control 0fh acgc cgain6 cgain5 cgain4 cgain3 cgain2 cgain1 cgain0 chrominance control 2 10h offu1 offu0 offv1 offv0 chbw lcbw2 lcbw1 lcbw0 mode/delay control 11h colo rtp1 hdel1 hdel0 rtp0 ydel2 ydel1 ydel0 rt signal control 12h rtse13 rtse12 rtse11 rtse10 rtse03 rtse02 rtse01 rtse00 rt/x port output control 13h rtce xrhs xrvs1 xrvs0 hlsel ofts2 ofts1 ofts0 analog/adc/compatibility control 14h cm99 uptcv aosl1 aosl0 xtoute oldsb apck1 apck0 vgate start, fid change 15h vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 vgate stop 16h vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 miscellaneous, vgate con?guration and msbs 17h llce llc2e [1] [1] [1] vgps vsto8 vsta8 raw data gain control 18h rawg7 rawg6 rawg5 rawg4 rawg3 rawg2 rawg1 rawg0 raw data offset control 19h rawo7 rawo6 rawo5 rawo4 rawo3 rawo2 rawo1 rawo0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 133 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec reserved 1ah to 1eh [1] [1] [1] [1] [1] [1] [1] [1] status byte video decoder (read only, oldsb = 0) 1fh intl hlvln fidt glimt glimb wipa copro rdcap status byte video decoder (read only, oldsb = 1) 1fh intl hlck fidt glimt glimb wipa sltca code reserved 20h to 2fh [1] [1] [1] [1] [1] [1] [1] [1] audio clock generator part: registers 30h to 3fh audio master clock cycles per ?eld 30h acpf7 acpf6 acpf5 acpf4 acpf3 acpf2 acpf1 acpf0 31h acpf15 acpf14 acpf13 acpf12 acpf11 acpf10 acpf9 acpf8 32h [1] [1] [1] [1] [1] [1] acpf17 acpf16 reserved 33h [1] [1] [1] [1] [1] [1] [1] [1] audio master clock nominal increment 34h acni7 acni6 acni5 acni4 acni3 acni2 acni1 acni0 35h acni15 acni14 acni13 acni12 acni11 acni10 acni9 acni8 36h [1] [1] acni21 acni20 acni19 acni18 acni17 acni16 reserved 37h [1] [1] [1] [1] [1] [1] [1] [1] clock ratio amxclk to asclk 38h [1] [1] sdiv5 sdiv4 sdiv3 sdiv2 sdiv1 sdiv0 clock ratio asclk to alrclk 39h [1] [1] lrdiv5 lrdiv4 lrdiv3 lrdiv2 lrdiv1 lrdiv0 audio clock generator basic setup 3ah [1] [1] [1] [1] apll amvr lrph scph reserved 3bh to 3fh [1] [1] [1] [1] [1] [1] [1] [1] general purpose vbi data slicer part: registers 40h to 7fh slicer control 1 40h [1] ham_n fce hunt_n [1] [1] [1] [1] lcr2 to lcr24 ( n=2to24) 41hto 57h lcrn_7 lcrn_6 lcrn_5 lcrn_4 lcrn_3 lcrn_2 lcrn_1 lcrn_0 programmable framing code 58h fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 horizontal offset for slicer 59h hoff7 hoff6 hoff5 hoff4 hoff3 hoff2 hoff1 hoff0 vertical offset for slicer 5ah voff7 voff6 voff5 voff4 voff3 voff2 voff1 voff0 field offset and msbs for horizontal and vertical offset 5bh foff recode [1] voff8 [1] hoff10 hoff9 hoff8 reserved (for testing) 5ch [1] [1] [1] [1] [1] [1] [1] [1] header and data identi?cation (did) code control 5dh fvref [1] did5 did4 did3 did2 did1 did0 sliced data identi?cation (sdid) code 5eh [1] [1] sdid5 sdid4 sdid3 sdid2 sdid1 sdid0 reserved 5fh [1] [1] [1] [1] [1] [1] [1] [1] table 141. i 2 c-bus receiver/transmitter overview continued register function subaddress d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 134 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec slicer status byte 0 (read only) 60h - fc8v fc7v vpsv ppv ccv - - slicer status byte 1 (read only) 61h - - f21_n ln8 ln7 ln6 ln5 ln4 slicer status byte 2 (read only) 62h ln3 ln2 ln1 ln0 dt3 dt2 dt1 dt0 reserved 63h to 7fh [1] [1] [1] [1] [1] [1] [1] [1] x port, i port and the scaler part: registers 80h to efh task independent global settings: 80h to 8fh global control 1 80h [1] smod teb tea icks3 icks2 icks1 icks0 reserved 81h and 82h [1] [1] [1] [1] [1] [1] [1] [1] x port i/o enable and output clock phase control 83h [1] [1] xpck1 xpck0 [1] xrqt xpe1 xpe0 i port signal de?nitions 84h idg01 idg00 idg11 idg10 idv1 idv0 idh1 idh0 i port signal polarities 85h iswp1 iswp0 illv ig0p ig1p irvp irhp idqp i port fifo ?ag control and arbitration 86h vitx1 vitx0 idg02 idg12 ffl1 ffl0 fel1 fel0 i port i/o enable, output clock and gated clock phase control 87h ipck3 ipck2 ipck1 ipck0 [1] [1] ipe1 ipe0 power save control 88h ch4en ch2en swrst dprog slm3 [1] slm1 slm0 reserved 89h to 8eh [1] [1] [1] [1] [1] [1] [1] [1] status information scaler part 8fh xtri itri ffil ffov prdon errof fidsci fidsco task a de?nition: registers 90h to bfh basic settings and acquisition window de?nition task handling control 90h conlh ofidc fskp2 fskp1 fskp0 rptsk strc1 strc0 x port formats and con?guration 91h conlv hldfv scsrc1 scsrc0 scrqe fsc2 fsc1 fsc0 x port input reference signal de?nitions 92h xfdv xfdh xdv1 xdv0 xcode xdh xdq xcks i port output formats and con?guration 93h icode i8_16 fysk foi1 foi0 fsi2 fsi1 fsi0 horizontal input window start 94h xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 95h [1] [1] [1] [1] xo11 xo10 xo9 xo8 horizontal input window length 96h xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 97h [1] [1] [1] [1] xs11 xs10 xs9 xs8 vertical input window start 98h yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 99h [1] [1] [1] [1] yo11 yo10 yo9 yo8 table 141. i 2 c-bus receiver/transmitter overview continued register function subaddress d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 135 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec vertical input window length 9ah ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 9bh [1] [1] [1] [1] ys11 ys10 ys9 ys8 horizontal output window length 9ch xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 9dh [1] [1] [1] [1] xd11 xd10 xd9 xd8 vertical output window length 9eh yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 9fh [1] [1] [1] [1] yd11 yd10 yd9 yd8 fir ?ltering and prescaling horizontal prescaling a0h [1] [1] xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 accumulation length a1h [1] [1] xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 prescaler dc gain and fir pre?lter control a2h pfuv1 pfuv0 pfy1 pfy0 xc2_1 xdcg2 xdcg1 xdcg0 reserved a3h [1] [1] [1] [1] [1] [1] [1] [1] luminance brightness control a4h brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast control a5h cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chrominance saturation control a6h satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 reserved a7h [1] [1] [1] [1] [1] [1] [1] [1] horizontal phase scaling horizontal luminance scaling increment a8h xscy7 xscy6 xscy5 xscy4 xscy3 xscy2 xscy1 xscy0 a9h [1] [1] [1] xscy12 xscy11 xscy10 xscy9 xscy8 horizontal luminance phase offset aah xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 reserved abh [1] [1] [1] [1] [1] [1] [1] [1] horizontal chrominance scaling increment ach xscc7 xscc6 xscc5 xscc4 xscc3 xscc2 xscc1 xscc0 adh [1] [1] [1] xscc12 xscc11 xscc10 xscc9 xscc8 horizontal chrominance phase offset aeh xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 reserved afh [1] [1] [1] [1] [1] [1] [1] [1] vertical scaling vertical luminance scaling increment b0h yscy7 yscy6 yscy5 yscy4 yscy3 yscy2 yscy1 yscy0 b1h yscy15 yscy14 yscy13 yscy12 yscy11 yscy10 yscy9 yscy8 vertical chrominance scaling increment b2h yscc7 yscc6 yscc5 yscc4 yscc3 yscc2 yscc1 yscc0 b3h yscc15 yscc14 yscc13 yscc12 yscc11 yscc10 yscc9 yscc8 vertical scaling mode control b4h [1] [1] [1] ymir [1] [1] [1] ymode reserved b5h to b7h [1] [1] [1] [1] [1] [1] [1] [1] table 141. i 2 c-bus receiver/transmitter overview continued register function subaddress d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 136 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec vertical chrominance phase offset 00 b8h ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 vertical chrominance phase offset 01 b9h ypc17 ypc16 ypc15 ypc14 ypc13 ypc12 ypc11 ypc10 vertical chrominance phase offset 10 bah ypc27 ypc26 ypc25 ypc24 ypc23 ypc22 ypc21 ypc20 vertical chrominance phase offset 11 bbh ypc37 ypc36 ypc35 ypc34 ypc33 ypc32 ypc31 ypc30 vertical luminance phase offset 00 bch ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 vertical luminance phase offset 01 bdh ypy17 ypy16 ypy15 ypy14 ypy13 ypy12 ypy11 ypy10 vertical luminance phase offset 10 beh ypy27 ypy26 ypy25 ypy24 ypy23 ypy22 ypy21 ypy20 vertical luminance phase offset 11 bfh ypy37 ypy36 ypy35 ypy34 ypy33 ypy32 ypy31 ypy30 task b de?nition registers c0h to efh basic settings and acquisition window de?nition task handling control c0h conlh ofidc fskp2 fskp1 fskp0 rptsk strc1 strc0 x port formats and con?guration c1h conlv hldfv scsrc1 scsrc0 scrqe fsc2 fsc1 fsc0 input reference signal de?nition c2h xfdv xfdh xdv1 xdv0 xcode xdh xdq xcks i port formats and con?guration c3h icode i8_16 fysk foi1 foi0 fsi2 fsi1 fsi0 horizontal input window start c4h xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 c5h [1] [1] [1] [1] xo11 xo10 xo9 xo8 horizontal input window length c6h xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 c7h [1] [1] [1] [1] xs11 xs10 xs9 xs8 vertical input window start c8h yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 c9h [1] [1] [1] [1] yo11 yo10 yo9 yo8 vertical input window length cah ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 cbh [1] [1] [1] [1] ys11 ys10 ys9 ys8 horizontal output window length cch xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 cdh [1] [1] [1] [1] xd11 xd10 xd9 xd8 vertical output window length ceh yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 cfh [1] [1] [1] [1] yd11 yd10 yd9 yd8 fir ?ltering and prescaling horizontal prescaling d0h [1] [1] xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 accumulation length d1h [1] [1] xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 prescaler dc gain and fir pre?lter control d2h pfuv1 pfuv0 pfy1 pfy0 xc2_1 xdcg2 xdcg1 xdcg0 reserved d3h [1] [1] [1] [1] [1] [1] [1] [1] table 141. i 2 c-bus receiver/transmitter overview continued register function subaddress d7 d6 d5 d4 d3 d2 d1 d0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 137 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] all unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. luminance brightness control d4h brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast control d5h cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chrominance saturation control d6h satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 reserved d7h [1] [1] [1] [1] [1] [1] [1] [1] horizontal phase scaling horizontal luminance scaling increment d8h xscy7 xscy6 xscy5 xscy4 xscy3 xscy2 xscy1 xscy0 d9h [1] [1] [1] xscy12 xscy11 xscy10 xscy9 xscy8 horizontal luminance phase offset dah xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 reserved dbh [1] [1] [1] [1] [1] [1] [1] [1] horizontal chrominance scaling increment dch xscc7 xscc6 xscc5 xscc4 xscc3 xscc2 xscc1 xscc0 ddh [1] [1] [1] xscc12 xscc11 xscc10 xscc9 xscc8 horizontal chrominance phase offset deh xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 reserved dfh [1] [1] [1] [1] [1] [1] [1] [1] vertical scaling vertical luminance scaling increment e0h yscy7 yscy6 yscy5 yscy4 yscy3 yscy2 yscy1 yscy0 e1h yscy15 yscy14 yscy13 yscy12 yscy11 yscy10 yscy9 yscy8 vertical chrominance scaling increment e2h yscc7 yscc6 yscc5 yscc4 yscc3 yscc2 yscc1 yscc0 e3h yscc15 yscc14 yscc13 yscc12 yscc11 yscc10 yscc9 yscc8 vertical scaling mode control e4h [1] [1] [1] ymir [1] [1] [1] ymode reserved e5h to e7h [1] [1] [1] [1] [1] [1] [1] [1] vertical chrominance phase offset 00 e8h ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 vertical chrominance phase offset 01 e9h ypc17 ypc16 ypc15 ypc14 ypc13 ypc12 ypc11 ypc10 vertical chrominance phase offset 10 eah ypc27 ypc26 ypc25 ypc24 ypc23 ypc22 ypc21 ypc20 vertical chrominance phase offset 11 ebh ypc37 ypc36 ypc35 ypc34 ypc33 ypc32 ypc31 ypc30 vertical luminance phase offset 00 ech ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 vertical luminance phase offset 01 edh ypy17 ypy16 ypy15 ypy14 ypy13 ypy12 ypy11 ypy10 vertical luminance phase offset 10 eeh ypy27 ypy26 ypy25 ypy24 ypy23 ypy22 ypy21 ypy20 vertical luminance phase offset 11 efh ypy37 ypy36 ypy35 ypy34 ypy33 ypy32 ypy31 ypy30 table 141. i 2 c-bus receiver/transmitter overview continued register function subaddress d7 d6 d5 d4 d3 d2 d1 d0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 138 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2 i 2 c-bus details 11.2.2.1 subaddress 00h 11.2.2.2 subaddress 01h the programming of the horizontal increment delay is used to match internal processing delays to the delay of the adc. use recommended position only. 11.2.2.3 subaddress 02h table 142. chip version (cv) identi?cation; 00h[7:4]; read only register function logic levels id7 id6 id5 id4 chip version (cv) cv3 cv2 cv1 cv0 table 143. horizontal increment delay; 01h[3:0] function idel3 idel2 idel1 idel0 no update 1111 minimum delay 1110 recommended position 1000 maximum delay 0000 table 144. analog input control 1 (aico1); 02h[7:0] bit description symbol value function 7 and 6 analog function select; see figure 16 fuse[1:0] 00 ampli?er plus anti-alias ?lter bypassed 01 ampli?er plus anti-alias ?lter bypassed 10 ampli?er active 11 ampli?er plus anti-alias ?lter active 5 and 4 update hysteresis for 9-bit gain; see figure 17 gudl[1:0] 00 off 01 1 lsb 10 2 lsb 11 3 lsb
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 139 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] to take full advantage of the y/c modes 6 to 9, the i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). 3 to 0 mode selection mode[3:0] 0000 mode 0 : cvbs (automatic gain) from ai11 (pin p13); see figure 53 0001 mode 1 : cvbs (automatic gain) from ai12 (pin p11); see figure 54 0010 mode 2 : cvbs (automatic gain) from ai21 (pin p10); see figure 55 0011 mode 3 : cvbs (automatic gain) from ai22 (pin p9); see figure 56 0100 mode 4 : cvbs (automatic gain) from ai23 (pin p7); see figure 57 0101 mode 5 : cvbs (automatic gain) from ai24 (pin p6); see figure 58 0110 mode 6 : y (automatic gain) from ai11 (pin p13) + c (gain adjustable via gai28 to gai20) from ai21 (pin p10) [1] ; see figure 59 0111 mode 7 : y (automatic gain) from ai12 (pin p11) + c (gain adjustable via gai28 to gai20) from ai22 (pin p9) [1] ; see figure 60 1000 mode 8 : y (automatic gain) from ai11 (pin p13) + c (gain adapted to y gain) from ai21 (pin p10) [1] ; see figure 61 1001 mode 9 : y (automatic gain) from ai12 (pin p11) + c (gain adapted to y gain) from ai22 (pin p9) [1] ; see figure 62 1010 to 1111 modes 10 to 15 : reserved fig 53. mode 0 cvbs (automatic gain) fig 54. mode 1 cvbs (automatic gain) table 144. analog input control 1 (aico1); 02h[7:0] continued bit description symbol value function mhb559 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma ai24 ai23 mhb560 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 140 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 55. mode 2 cvbs (automatic gain) fig 56. mode 3 cvbs (automatic gain) fig 57. mode 4 cvbs (automatic gain) fig 58. mode 5 cvbs (automatic gain) i 2 c-bus bit byps (subaddress 09h, bit d7) should be set to logic 1 (full luminance bandwidth). i 2 c-bus bit byps (subaddress 09h, bit d7) should be set to logic 1 (full luminance bandwidth). fig 59. mode 6 y + c (gain channel 2 adjusted via gai2) fig 60. mode 7 y + c (gain channel 2 adjusted via gai2) i 2 c-bus bit byps (subaddress 09h, bit d7) should be set to logic 1 (full luminance bandwidth). i 2 c-bus bit byps (subaddress 09h, bit d7) should be set to logic 1 (full luminance bandwidth). fig 61. mode 8 y + c (gain channel 2 adapted to y gain) fig 62. mode 9 y + c (gain channel 2 adapted to y gain) mhb561 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb562 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb563 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb564 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb565 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb566 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb567 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 mhb568 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 141 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.4 subaddress 03h [1] hlnrs = 1 should not be used in combination with wpoff = 0. 11.2.2.5 subaddress 04h 11.2.2.6 subaddress 05h table 145. analog input control 2 (aico2); 03h[6:0] bit description symbol value function 6 hl not reference select hlnrs 0 normal clamping if decoder is in unlocked state 1 [1] reference select if decoder is in unlocked state 5 agc hold during vertical blanking period vbsl 0 short vertical blanking (agc disabled during equalization and serration pulses) 1 long vertical blanking (agc disabled from start of pre-equalization pulses until start of active video (line 22 for 60 hz, line 24 for 50 hz) 4 white peak control off wpoff 0 [1] white peak control active 1 white peak control off 3 automatic gain control integration holdg 0 agc active 1 agc integration hold (freeze) 2 gain control ?x gafix 0 automatic gain controlled by mode3 to mode0 1 gain is user programmable via gai[17:10] and gai[27:20] 1 static gain control channel 2 sign bit gai28 see t ab le 147 0 static gain control channel 1 sign bit gai18 see t ab le 146 table 146. analog input control 3 (aico3); static gain control channel 1; 03h[0] and 04h[7:0] decimal value gain (db) sign bit 03h[0] control bits 7 to 0 gai18 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 0... - 30 00000000 ...144 0 0 1 0010000 145... 0 0 1 0010001 ...511 +6 1 1 1111111 table 147. analog input control 4 (aico4); static gain control channel 2; 03h[1] and 05h[7:0] decimal value gain (db) sign bit 03h[1] control bits 7 to 0 gai28 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 0... - 30 00000000 ...144 0 0 1 0010000 145... 0 0 1 0010001 ...511 +6 1 1 1111111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 142 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.7 subaddress 06h 11.2.2.8 subaddress 07h 11.2.2.9 subaddress 08h table 148. horizontal sync start; 06h[7:0] delay time (step size = 8/llc) control bits 7 to 0 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 - 128... - 109 (50 hz) forbidden (outside available central counter range) - 128... - 108 (60 hz) forbidden (outside available central counter range) - 108 (50 hz)... 1 0 0 1 0 1 0 0 - 107 (60 hz)... 1 0 0 1 0 1 0 1 ...108 (50 hz) 0 1 1 0 1 1 0 0 ...107 (60 hz) 0 1 1 0 1 0 1 1 109...127 (50 hz) forbidden (outside available central counter range) 108...127 (60 hz) table 149. horizontal sync stop; 07h[7:0] delay time (step size = 8/llc) control bits 7 to 0 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 - 128... - 109 (50 hz) forbidden (outside available central counter range) - 128... - 108 (60 hz) forbidden (outside available central counter range) - 108 (50 hz)... 1 0 0 1 0 1 0 0 - 107 (60 hz)... 1 0 0 1 0 1 0 1 ...108 (50 hz) 0 1 1 0 1 1 0 0 ...107 (60 hz) 0 1 1 0 1 0 1 1 109...127 (50 hz) forbidden (outside available central counter range) 108...127 (60 hz) forbidden (outside available central counter range) table 150. sync control; 08h[7:0] bit description symbol value function 7 automatic ?eld detection aufd 0 ?eld state directly controlled via fsel 1 automatic ?eld detection; recommended setting 6 ?eld selection; active if aufd = 0 fsel 0 50 hz, 625 lines 1 60 hz, 525 lines 5 forced odd/even toggle foet 0 odd/even signal toggles only with interlaced source 1 odd/even signal toggles ?eldwise even if source is non-interlaced
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 143 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.10 subaddress 09h 4 and 3 horizontal time constant selection htc[1:0] 00 tv mode, recommended for poor quality tv signals only; do not use for new applications 01 vtr mode, recommended if a de?ection control circuit is directly connected to the SAA7108AE; saa7109ae 10 reserved 11 fast locking mode; recommended setting 2 horizontal pll hpll 0 pll closed 1 pll open; horizontal frequency ?xed 1 and 0 vertical noise reduction vnoi[1:0] 00 normal mode; recommended setting 01 fast mode, applicable for stable sources only; automatic ?eld detection (aufd) must be disabled 10 free running mode 11 vertical noise reduction bypassed table 150. sync control; 08h[7:0] continued bit description symbol value function table 151. luminance control; 09h[7:0] bit description symbol value function 7 chrominance trap/comb ?lter bypass byps 0 chrominance trap or luminance comb ?lter active; default for cvbs mode 1 chrominance trap or luminance comb ?lter bypassed; default for s-video mode 6 adaptive luminance comb ?lter ycomb 0 disabled (= chrominance trap enabled, if byps = 0) 1 active, if byps = 0 5 processing delay in non comb ?lter mode ldel 0 processing delay is equal to internal pipe-lining delay 1 one (ntsc standards) or two (pal standards) video lines additional processing delay 4 remodulation bandwidth for luminance; see figure 22 to figure 25 lubw 0 small remodulation bandwidth (narrow chrominance notch t higher luminance bandwidth) 1 large remodulation bandwidth (wider chrominance notch t smaller luminance bandwidth)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 144 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.11 subaddress 0ah 3 to 0 sharpness control, luminance ?lter characteristic; see figure 26 lufi[3:0] 0001 resolution enhancement ?lter 8.0 db at 4.1 mhz 0010 resolution enhancement ?lter 6.8 db at 4.1 mhz 0011 resolution enhancement ?lter 5.1 db at 4.1 mhz 0100 resolution enhancement ?lter 4.1 db at 4.1 mhz 0101 resolution enhancement ?lter 3.0 db at 4.1 mhz 0110 resolution enhancement ?lter 2.3 db at 4.1 mhz 0111 resolution enhancement ?lter 1.6 db at 4.1 mhz 0000 plain 1000 low-pass ?lter 2 db at 4.1 mhz 1001 low-pass ?lter 3 db at 4.1 mhz 1010 low-pass ?lter 3 db at 3.3 mhz; 4 db at 4.1 mhz 1011 low-pass ?lter 3 db at 2.6 mhz; 8 db at 4.1 mhz 1100 low-pass ?lter 3 db at 2.4 mhz; 14 db at 4.1 mhz 1101 low-pass ?lter 3 db at 2.2 mhz; notch at 3.4 mhz 1110 low-pass ?lter 3 db at 1.9 mhz; notch at 3.0 mhz 1111 low-pass ?lter 3 db at 1.7 mhz; notch at 2.5 mhz table 151. luminance control; 09h[7:0] continued bit description symbol value function table 152. luminance brightness control: decoder part; 0ah[7:0] offset control bits 7 to 0 dbri7 dbri6 dbri5 dbri4 dbri3 dbri2 dbri1 dbri0 255 (bright) 1 1 1 1 1 1 1 1 128 (itu level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 145 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.12 subaddress 0bh 11.2.2.13 subaddress 0ch 11.2.2.14 subaddress 0dh table 153. luminance contrast control: decoder part; 0bh[7:0] gain control bits 7 to 0 dcon7 dcon6 dcon5 dcon4 dcon3 dcon2 dcon1 dcon0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.063 (itu level) 0 1 0 0 0 1 0 0 1.0 01000000 0 (luminance off) 0 0 0 0 0 0 0 0 - 1 (inverse luminance) 11000000 - 2 (inverse luminance) 10000000 table 154. chrominance saturation control: decoder part; 0ch[7:0] gain control bits 7 to 0 dsat7 dsat6 dsat5 dsat4 dsat3 dsat2 dsat1 dsat0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.0 (itu level) 0 1 0 0 0 0 0 0 0 (color off) 0 0 0 0 0 0 0 0 - 1 (inverse chrominance) 11000000 - 2 (inverse chrominance) 10000000 table 155. chrominance hue control; 0dh[7:0] hue phase (deg) control bits 7 to 0 huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 +178.6... 0 1 1 1 1 1 1 1 ...0... 0 0 0 0 0 0 0 0 ... - 180 10000000
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 146 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.15 subaddress 0eh table 156. chrominance control 1; 0eh[7:0] bit description symbol value function 7 clear dto cdto 0 disabled 1 every time cdto is set, the internal subcarrier dto phase is reset to 0 and the rtco output generates a logic 0 at time slot 68 (see document how to use real time control (rtc) , available on request). so an identical subcarrier phase can be generated by an external device (e.g. an encoder); if a dto reset is programmed via cdto it has always to be executed in the following order: 1. set cdto = 0 2. set cdto = 1 6 to 4 color standard selection cstd[2:0] 000 50 hz/625 lines: pal bgdhi (4.43 mhz) 60 hz/525 lines: ntsc m (3.58 mhz) 001 50 hz/625 lines: ntsc 4.43 (50 hz) 60 hz/525 lines: pal 4.43 (60 hz) 010 50 hz/625 lines: combination-pal n (3.58 mhz) 60 hz/525 lines: ntsc 4.43 (60 hz) 011 50 hz/625 lines: ntsc n (3.58 mhz) 60 hz/525 lines: pal m (3.58 mhz) 100 50 hz/625 lines: reserved 60 hz/525 lines: ntsc-japan (3.58 mhz) 101 50 hz/625 lines: secam 60 hz/525 lines: reserved 110 reserved; do not use 111 reserved; do not use 3 disable chrominance vertical ?lter and pal phase error correction dcvf 0 chrominance vertical ?lter and pal phase error correction on (during active video lines) 1 chrominance vertical ?lter and pal phase error correction permanently off 2 fast color time constant fctc 0 nominal time constant 1 fast time constant for special applications (high quality input source, fast chroma lock required, automatic standard detection off) 0 adaptive chrominance comb ?lter ccomb 0 disabled 1 active
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 147 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.16 subaddress 0fh 11.2.2.17 subaddress 10h 11.2.2.18 subaddress 11h table 157. chrominance gain control; 0fh[7:0] bit description symbol value function 7 automatic chrominance gain control acgc 0 on 1 programmable gain via cgain6 to cgain0; need to be set for secam standard 6 to 0 chrominance gain value (if acgc is set to logic 1) cgain[6:0] 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5) table 158. chrominance control 2; 10h[7:0] bit description symbol value function 7 and 6 ?ne offset adjustment b - y component offu[1:0] 00 0 lsb 01 1 4 lsb 10 1 2 lsb 11 3 4 lsb 5 and 4 ?ne offset adjustment r - y component offv[1:0] 00 0 lsb 01 1 4 lsb 10 1 2 lsb 11 3 4 lsb 3 chrominance bandwidth; see figure 20 and figure 21 chbw 0 small 1 wide 2 to 0 combined luminance and chrominance bandwidth adjustment; see figure 20 to figure 26 lcbw[2:0] 000 smallest chrominance bandwidth and largest luminance bandwidth ... ... to ... 111 largest chrominance bandwidth and smallest luminance bandwidth table 159. mode/delay control; 11h[7:0] bit description symbol value function 7 color on colo 0 automatic color killer enabled 1 color forced on 6 polarity of rts1 output signal rtp1 0 non-inverted 1 inverted 5 and 4 ?ne position of hs (steps in 2/llc) hdel[1:0] 00 0 01 1 10 2 11 3
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 148 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.19 subaddress 12h 3 polarity of rts0 output signal rtp0 0 non-inverted 1 inverted 2 to 0 luminance delay compensation (steps in 2/llc) ydel[2:0] 100 - 4... 000 ...0... 011 ...3 table 159. mode/delay control; 11h[7:0] continued bit description symbol value function table 160. rt signal control: rts0 output; 12h[3:0] the polarity of any signal on rts0 can be inverted via rtp0[11h[3]]. rts0 output rtse03 rtse02 rtse01 rtse00 3-state 0000 constant low 0001 cref (13.5 mhz toggling pulse; see figure 35 ) 0010 cref2 (6.75 mhz toggling pulse; see figure 35 ) 0011 hl; horizontal lock indicator [1] : hl = 0: unlocked hl = 1: locked 0100 vl; vertical and horizontal lock: vl = 0: unlocked vl = 1: locked 0101 dl; vertical and horizontal lock and color detected: dl = 0: unlocked dl = 1: locked 0110 reserved 0111 href, horizontal reference signal; indicates 720 pixels valid data on the expansion port. the positive slope marks the beginning of a new active line. href is also generated during the vertical blanking interval (see figure 35 ). 1000 hs: programmable width in llc8 steps via hsb[7:0] 06h[7:0] and hss[7:0] 07h[7:0] fine position adjustment in llc2 steps via hdel[1:0] 11h[5:4] (see figure 35 ) 1001 hq; href gated with vgate 1010 reserved 1011 v123; vertical sync (see vertical timing diagrams figure 33 and figure 34 ) 1100 vgate; programmable via vsta[8:0] 17h[0] 15h[7:0], vsto[8:0] 17h[1] 16h[7:0] and vgps[17h[2]] 1101 lsbs of the 9-bit adcs 1110 fid; position programmable via vsta[8:0] 17h[0] 15h[7:0] (see vertical timing diagrams figure 33 and figure 34 ) 1111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 149 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] function of hl is selectable via hlsel[13h[3]]: a) hlsel = 0: hl is standard horizontal lock indicator. b) hlsel = 1: hl is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. vcrs). [1] function of hl is selectable via hlsel[13h[3]]: a) hlsel = 0: hl is standard horizontal lock indicator. b) hlsel = 1: hl is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. vcrs). table 161. rt signal control: rts1 output; 12h[7:4] the polarity of any signal on rts1 can be inverted via rtp1[11h[6]]. rts1 output rtse13 rtse12 rtse11 rtse10 3-state 0000 constant low 0001 cref (13.5 mhz toggling pulse; see figure 35 ) 0010 cref2 (6.75 mhz toggling pulse; see figure 35 ) 0011 hl; horizontal lock indicator [1] : hl = 0: unlocked hl = 1: locked 0100 vl; vertical and horizontal lock: vl = 0: unlocked vl = 1: locked 0101 dl; vertical and horizontal lock and color detected: dl = 0: unlocked dl = 1: locked 0110 reserved 0111 href, horizontal reference signal; indicates 720 pixels valid data on the expansion port. the positive slope marks the beginning of a new active line. href is also generated during the vertical blanking interval (see figure 35 ). 1000 hs: programmable width in llc8 steps via hsb[7:0] 06h[7:0] and hss[7:0] 07h[7:0] fine position adjustment in llc2 steps via hdel[1:0] 11h[5:4] (see figure 35 ) 1001 hq; href gated with vgate 1010 reserved 1011 v123; vertical sync (see vertical timing diagrams figure 33 and figure 34 ) 1100 vgate; programmable via vsta[8:0] 17h[0] 15h[7:0], vsto[8:0] 17h[1] 16h[7:0] and vgps[17h[2]] 1101 reserved 1110 fid; position programmable via vsta[8:0] 17h[0] 15h[7:0] (see vertical timing diagrams figure 33 and figure 34 ) 1111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 150 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.20 subaddress 13h table 162. rt/x port output control; 13h[7:0] bit description symbol value function 7 rtco output enable rtce 0 3-state 1 enabled 6 x port xrh output selection xrhs 0 href (see figure 35 ) 1 hs: programmable width in llc8 steps via hsb[7:0] 06h[7:0] and hss[7:0] 07h[7:0] fine position adjustment in llc2 steps via hdel[1:0] 11h[5:4] (see figure 35 ) 5 and 4 x port xrv output selection xrvs[1:0] 00 v123 (see figure 33 and figure 34 ) 01 itu 656 related ?eld id (see figure 33 and figure 34 ) 10 inverted v123 11 inverted itu 656 related ?eld id 3 horizontal lock indicator selection hlsel 0 copy of inverted hlck status bit (default) 1 fast horizontal lock indicator (for special applications only) 2 to 0 xpd7 to xpd0 (port output format selection); see section 10.4 ofts[2:0] 000 itu 656 001 itu 656-like format with modi?ed ?eld blanking according to vgate position (programmable via vsta[8:0] 17h[0] 15h[7:0], vsto[8:0] 17h[1] 16h[7:0] and vgps[17h[2]]) 010 y-c b -c r 4 : 2 : 2 8-bit format (no sav/eav codes inserted) 011 reserved 100 multiplexed ad2/ad1 bypass (bits 8 to 1) dependent on mode settings (see section 11.2.2.3 ); if both adcs are selected ad2 is output at cref = 1 and ad1 is output at cref = 0 101 multiplexed ad2/ad1 bypass (bits 7 to 0) dependent on mode settings (see section 11.2.2.3 ); if both adcs are selected ad2 is output at cref = 1 and ad1 is output at cref = 0 110 reserved 111 multiplexed adc msb/lsb bypass dependent on mode settings; only one adc should be selected at a time; adx8 to adx1 are outputs at cref = 1 and adx7 to adx0 are outputs at cref = 0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 151 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.21 subaddress 14h 11.2.2.22 subaddress 15h table 163. analog/adc/compatibility control; 14h[7:0] bit description symbol value function 7 compatibility bit for saa7199 cm99 0 off (default) 1 on (to be set only if saa7199 is used for re-encoding in conjunction with rtco active ) 6 update time interval for agc value uptcv 0 horizontal update (once per line) 1 vertical update (once per ?eld) 5 and 4 analog test select aosl[1:0] 00 aout connected to internal test point 1 01 aout connected to input ad1 10 aout connected to input ad2 11 aout connected to internal test point 2 3 xtoutd output enable xtoute 0 pin p4 (xtoutd) 3-stated 1 pin p4 (xtoutd) enabled 2 decoder status byte selection; see t ab le 169 oldsb 0 standard 1 backward compatibility to saa7112 1 and 0 adc sample clock phase delay apck[1:0] 00 application dependent 01 application dependent 10 application dependent 11 application dependent table 164. vgate start; fid polarity change; 17h[0] and 15h[7:0] start of vgate pulse (low-to-high transition) and polarity change of fid pulse, vgps = 0; see figure 33 and figure 34 . field frame line counting decimal value msb 17h[0] control bits 7 to 0 vsta8 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 50 hz 1st 1 312 1 0 0 1 1 1 0 0 0 2nd 314 1st 2 0... 0 0 0 0 0 0 0 0 0 2nd 315 1st 312 ...310 1 0 0 1 1 0 1 1 1 2nd 625 60 hz 1st 4 262 1 0 0 0 0 0 1 1 0 2nd 267 1st 5 0... 0 0 0 0 0 0 0 0 0 2nd 268 1st 265 ...260 1 0 0 0 0 0 1 0 1 2nd 3
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 152 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.23 subaddress 16h 11.2.2.24 subaddress 17h 11.2.2.25 subaddress 18h table 165. vgate stop; 17h[1] and 16h[7:0] stop of vgate pulse (high-to-low transition), vgps = 0; see figure 33 and figure 34 . field frame line counting decimal value msb 17h[1] control bits 7 to 0 vsto8 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 50hz1st1 3121 00111000 2nd 314 1st 2 0... 0 00000000 2nd 315 1st 312 ...310 1 00110111 2nd 625 60hz1st4 2621 00000110 2nd 267 1st 5 0... 0 00000000 2nd 268 1st 265 ...260 1 00000101 2nd 3 table 166. miscellaneous/vgate msbs; 17h[7:6] and 17h[2:0] bit description symbol value function 7 llc output enable llce 0 enable 1 3-state 6 llc2 output enable llc2e 0 enable 1 3-state 2 alternative vgate position vgps 0 vgate position according to t ab le 164 and t ab le 165 1 vgate occurs one line earlier during ?eld 2 1 msb vgate stop vsto8 see t ab le 165 0 msb vgate start vsta8 see t ab le 164 table 167. raw data gain control; rawg[7:0] 18h[7:0]; see figure 28 gain control bits 7 to 0 rawg7 rawg6 rawg5 rawg4 rawg3 rawg2 rawg1 rawg0 255 (double amplitude) 0 1 1 1 1 1 1 1 128 (nominal level) 0 1 0 0 0 0 0 0 0 (off) 0 0 0 0 0 0 0 0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 153 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.2.26 subaddress 19h 11.2.2.27 subaddress 1fh table 168. raw data offset control; rawo[7:0] 19h[7:0]; see figure 28 offset control bits 7 to 0 rawo7 rawo6 rawo5 rawo4 rawo3 rawo2 rawo1 rawo0 - 128lsb 00000000 0lsb 10000000 +128 lsb 1 1 1 1 1 1 1 1 table 169. status byte video decoder; 1fh[7:0]; read only register bit description i 2 c-bus control bit oldsb 14h[2] value function 7 status bit for interlace detection intl - 0 non-interlaced 1 interlaced 6 status bit for horizontal and vertical loop hlvln 0 0 both loops locked 1 unlocked status bit for locked horizontal frequency hlck 1 0 locked 1 unlocked 5 identi?cation bit for detected ?eld frequency fidt - 0 50 hz 160hz 4 gain value for active luminance channel is limited; maximum (top) glimt - 0 not active 1 active 3 gain value for active luminance channel is limited; minimum (bottom) glimb - 0 not active 1 active 2 white peak loop is activated wipa - 0 not active 1 active 1 copy protected source detected according to macrovision version up to 7.01 copro 0 0 not active 1 active slow time constant active in wipa mode sltca 1 0 not active 1 active 0 ready for capture (all internal loops locked) rdcap 0 0 not active 1 active color signal in accordance with selected standard has been detected code 1 0 not active 1 active
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 154 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.3 programming register audio clock generation see equations in section 9.6 and examples in t ab le 35 and t ab le 36 . 11.2.3.1 subaddresses 30h to 32h 11.2.3.2 subaddresses 34h to 36h 11.2.3.3 subaddress 38h 11.2.3.4 subaddress 39h 11.2.3.5 subaddress 3ah table 170. audio master clock (amclk) cycles per ?eld subaddress control bits 7 to 0 30h acpf7 acpf6 acpf5 acpf4 acpf3 acpf2 acpf1 acpf0 31h acpf15 acpf14 acpf13 acpf12 acpf11 acpf10 acpf9 acpf8 32h - - - - - - acpf17 acpf16 table 171. audio master clock (amclk) nominal increment subaddress control bits 7 to 0 34h acni7 acni6 acni5 acni4 acni3 acni2 acni1 acni0 35h acni15 acni14 acni13 acni12 acni11 acni10 acni9 acni8 36h - - acni21 acni20 acni19 acni18 acni17 acni16 table 172. clock ratio audio master clock (amxclk) to serial bit clock (asclk) subaddress control bits 7 to 0 38h - - sdiv5 sdiv4 sdiv3 sdiv2 sdiv1 sdiv0 table 173. clock ratio serial bit clock (asclk) to channel select clock (alrclk) subaddress control bits 7 to 0 39h - - lrdiv5 lrdiv4 lrdiv3 lrdiv2 lrdiv1 lrdiv0 table 174. audio clock control; 3ah[3:0] bit description symbol value function 3 audio pll modes apll 0 pll active, amclk is ?eld-locked 1 pll open, amclk is free-running 2 audio master clock vertical reference amvr 0 vertical reference pulse is taken from internal decoder 1 vertical reference is taken from xrv input (expansion port) 1 alrclk phase lrph 0 alrclk edges triggered by falling edges of asclk 1 alrclk edges triggered by rising edges of asclk 0 asclk phase scph 0 asclk edges triggered by falling edges of amclk 1 asclk edges triggered by rising edges of amclk
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 155 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.4 programming register vbi data slicer 11.2.4.1 subaddress 40h 11.2.4.2 subaddresses 41h to 57h table 175. slicer control 1; 40h[6:4] bit description symbol value function 6 hamming check ham_n 0 hamming check for 2 bytes after framing code, dependent on data type (default) 1 no hamming check 5 framing code error fce 0 one framing code error allowed 1 no framing code errors allowed 4 amplitude searching hunt_n 0 amplitude searching active (default) 1 amplitude searching stopped table 176. line control register; lcr2 to lcr24 (41h to 57h) see section 9.2 and section 9.4 . name description framing code bits 7 to 4 (41h to 57h) bits 3 to 0 (41h to 57h) dt[3:0] 62h[3:0] (?eld 1) dt[3:0] 62h[3:0] (?eld 2) wst625 teletext eurowst, ccst 27h 0000 0000 cc625 european closed caption 001 0001 0001 vps video programming service 9951h 0010 0010 wss wide screen signalling bits 1e 3c1fh 0011 0011 wst525 us teletext (wst) 27h 0100 0100 cc525 us closed caption (line 21) 001 0101 0101 test line video component signal, vbi region - 0110 0110 intercast raw data - 0111 0111 general text teletext programmable 1000 1000 vitc625 vitc/ebu time codes (europe) programmable 1001 1001 vitc525 vitc/smpte time codes (usa) programmable 1010 1010 reserved reserved - 1011 1011 nabts us nabts - 1100 1100 japtext moji (japanese) programmable (a7h) 1101 1101 jfs japanese format switch (l20/22) programmable 1110 1110 active video video component signal, active video region (default) - 1111 1111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 156 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.4.3 subaddress 58h 11.2.4.4 subaddress 59h 11.2.4.5 subaddress 5ah 11.2.4.6 subaddress 5bh 11.2.4.7 subaddress 5dh table 177. programmable framing code; slicer set 58h[7:0]; see t ab le 28 and t ab le 176 framing code for programmable data types control bits 7 to 0 default value fc[7:0] = 40h table 178. horizontal offset for slicer; slicer set 59h and 5bh horizontal offset control bits 5bh[2:0] control bits 59h[7:0] recommended value hoff[10:8] = 3h hoff[7:0] = 47h table 179. vertical offset for slicer; slicer set 5ah and 5bh vertical offset control bit 5bh[4] control bits 5ah[7:0] voff8 voff[7:0] minimum value 0 0 00h maximum value 312 1 38h value for 50 hz 625 lines input 0 03h value for 60 hz 525 lines input 0 06h table 180. field offset, and msbs for horizontal and vertical offsets; slicer set 5bh[7:6] see section 11.2.4.4 and section 11.2.4.5 for hoff[10:8] 5bh[2:0] and voff8[5bh[4]]. bit description symbol value function 7 ?eld offset foff 0 no modi?cation of internal ?eld indicator (default for 50 hz 625 lines input sources) 1 invert ?eld indicator (default for 60 hz 525 lines input sources) 6 recode recode 0 leave data unchanged (default) 1 convert 00h and ffh data bytes into 03h and fch table 181. header and data identi?cation (did; itu 656) code control; slicer set 5dh[7:0] bit description symbol value function 7 ?eld id and v-blank selection for text output (f and v reference selection) fvref 0 f and v output of slicer is lcr table dependent 1 f and v output is taken from decoder real-time signals even_itu and vblnk_itu 5to0 default; did[5:0] = 00h did[5:0] 00 0000 anc header framing ; see figure 42 and t ab le 34 special cases of did programming 11 1110 did[5:0] = 3eh sav/eav framing, with fvref = 1 11 1111 did[5:0] = 3fh sav/eav framing, with fvref = 0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 157 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.4.8 subaddress 5eh 11.2.4.9 subaddress 60h 11.2.4.10 subaddresses 61h and 62h 11.2.5 programming register interfaces and scaler part 11.2.5.1 subaddress 80h [1] x = dont care. table 182. sliced data identi?cation (sdid) code; slicer set 5eh[5:0] bit description symbol value function 5 to 0 sdid codes sdid[5:0] 00h default table 183. slicer status byte 0; 60h[6:2]; read only register bit description symbol value function 6 framing code valid fc8v 0 no framing code (0 error) in the last frame detected 1 framing code with 0 error detected 5 framing code valid fc7v 0 no framing code (1 error) in the last frame detected 1 framing code with 1 error detected 4 vps valid vpsv 0 no vps in the last frame 1 vps detected 3 palplus valid ppv 0 no palplus in the last frame 1 palplus detected 2 closed caption valid ccv 0 no closed caption in the last frame 1 closed caption detected table 184. slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only registers subaddress bit symbol description 61h 5 f21_n ?eld id as seen by the vbi slicer; for ?eld 1: bi t5=0 4 to 0 ln[8:4] line number 62h 7 to 4 ln[3:0] line number 3 to 0 dt[3:0] data type; according to t ab le 28 table 185. global control 1; global set 80h[6:4] [1] swrst moved to subaddress 88h[5]. task enable control control bits 6 to 4 smod teb tea task of register set a is disabled x x 0 task of register set a is enabled x x 1 task of register set b is disabled x 0 x task of register set b is enabled x 1 x the scaler window de?nes the f and v timing of the scaler output 0 x x vbi data slicer de?nes the f and v timing of the scaler output 1 x x
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 158 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. [2] although the iclk i/o is independent of icks2 and icks3, this selection can only be used if icks2 = 1. 11.2.5.2 subaddresses 83h to 87h [1] x = dont care. table 186. global control 1; global set 80h[3:0] [1] i port and scaler back-end clock selection control bits 3 to 0 icks3 icks2 icks1 icks0 iclk output and back-end clock is line-locked clock llc from decoder xx0 0 iclk output and back-end clock is xclk from x port x x 0 1 iclk output is llc and back-end clock is llc2 clock x x [2] 10 back-end clock is the iclk input x x 1 1 idq pin carries the data quali?er x 0 x x idq pin carries a gated back-end clock (idq and clk) x 1 x x idq generation only for valid data 0 x x x idq quali?es valid data inside the scaling region and all data outside the scaling region 1 xxx table 187. x port i/o enable and output clock phase control; global set 83h[5:4] output clock phase control control bits 5 and 4 xpck1 xpck0 xclk default output phase, recommended value 00 xclk output inverted 0 1 xclk phase shifted by approximately 3 ns 1 0 xclk output inverted and shifted by approximately 3 ns 1 1 table 188. x port i/o enable and output clock phase control; global set 83h[2:0] [1] x port i/o enable control bits 2 to 0 xrqt xpe1 xpe0 x port output is disabled by software x 0 0 x port output is enabled by software x 0 1 x port output is enabled by pin xtri at logic 0 x 1 0 x port output is enabled by pin xtri at logic 1 x 1 1 xrdy output signal is a/b task ?ag from event handler (a = 1) 0 x x xrdy output signal is ready signal from scaler path (xrdy = 1 means the SAA7108AE; saa7109ae is ready to receive data) 1xx
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 159 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. table 189. i port signal de?nitions; global set 84h[7:6] and 86h[5] i port signal de?nitions control bits 86h[5] 84h[7:6] idg02 idg01 idg00 igp0 is output ?eld id, as de?ned by ofidc[90h[6]] 0 0 0 igp0 is a/b task ?ag, as de?ned by conlh[90h[7]] 0 0 1 igp0 is sliced data ?ag, framing the sliced vbi data at the i port 0 1 0 igp0 is set to logic 0 (default polarity) 011 igp0 is the output fifo almost ?lled ?ag 1 0 0 igp0 is the output fifo over?ow ?ag 1 0 1 igp0 is the output fifo almost full ?ag, level to be programmed in subaddress 86h 110 igp0 is the output fifo almost empty ?ag, level to be programmed in subaddress 86h 111 table 190. i port signal de?nitions; global set 84h[5:4] and 86h[4] i port signal de?nitions control bits 86h[4] 84h[5:4] idg12 idg11 idg10 igp1 is output ?eld id, as de?ned by ofidc[90h[6]] 0 0 0 igp1 is a/b task ?ag, as de?ned by conlh[90h[7]] 0 0 1 igp1 is sliced data ?ag, framing the sliced vbi data at the i port 0 1 0 igp1 is set to logic 0 (default polarity) 011 igp1 is the output fifo almost ?lled ?ag 1 0 0 igp1 is the output fifo over?ow ?ag 1 0 1 igp1 is the output fifo almost full ?ag, level to be programmed in subaddress 86h 110 igp1 is the output fifo almost empty ?ag, level to be programmed in subaddress 86h 111 table 191. i port output signal de?nitions; global set 84h[3:0] [1] i port output signal de?nitions control bits 3 to 0 idv1 idv0 idh1 idh0 igph is a h gate signal, framing the scaler output x x 0 0 igph is an extended h gate (framing h gate during scaler output and scaler input h reference outside the scaler window) xx0 1 igph is a horizontal trigger pulse, on active going edge of h gate x x 1 0 igph is a horizontal trigger pulse, on active going edge of extended h gate xx1 1 igpv is a v gate signal, framing scaled output lines 0 0 x x igpv is the v reference signal from scaler input 0 1 x x igpv is a vertical trigger pulse, derived from v gate 1 0 x x igpv is a vertical trigger pulse derived from input v reference 1 1 x x
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 160 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. [1] x = dont care. [1] x = dont care. table 192. x port signal de?nitions text slicer; global set 85h[7:5] [1] x port signal de?nitions text slicer control bits 7 to 5 iswp1 iswp0 illv video data limited to range 1 to 254 x x 0 video data limited to range 8 to 247 x x 1 double word byte swap, in?uences serial output timing d0 d1 d2 d3 t ff 00 00 sav c b 0y0c r 0y1 00x d1 d0 d3 d2 t 00 ff sav 00 y0 c b 0y1c r 001x d2 d3 d0 d1 t 00 sav ff 00 c r 0y1c b 0y0 1 0 x d3 d2 d1 d0 t sav0000ffy1c r 0y0c b 011x table 193. i port reference signal polarities; global set 85h[4:0] [1] i port reference signal polarities control bits 4 to 0 ig0p ig1p irvp irhp idqp idq at default polarity (1 = active) xxxx0 idq is inverted xxxx1 igph at default polarity (1 = active) xxx0 x igph is inverted xxx1 x igpv at default polarity (1 = active) x x 0 x x igpv is inverted x x 1 x x igp1 at default polarity x 0 x x x igp1 is inverted x 1 x x x igp0 at default polarity 0 x x x x igp0 is inverted 1 x x x x table 194. i port fifo ?ag control and arbitration; global set 86h[7:4] [1] function control bits 7 to 4 vitx1 vitx0 idg02 idg12 see subaddress 84h: idg11 and idg10 x x x 0 xxx1 see subaddress 84h: idg01 and idg00 x x 0 x xx1 x i port signal de?nitions i port data output inhibited 0 0 x x only video data is transferred 0 1 x x only text data is transferred (no eav, sav will occur) 1 0 x x text and video data is transferred, text has priority 1 1 x x
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 161 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. [1] x = dont care. [2] ipck3 and ipck2 only affects the gated clock (subaddress 80h, bit icks2 = 1). table 195. i port fifo ?ag control and arbitration; global set 86h[3:0] [1] i port fifo ?ag control and arbitration control bits 3 to 0 ffl1 ffl0 fel1 fel0 fae fifo ?ag almost empty level < 16 double words x x 0 0 < 8 double words x x 0 1 < 4 double words x x 1 0 0 double words x x 1 1 faf fifo ?ag almost full level 3 16 double words 0 0 x x 3 24 double words 0 1 x x 3 28 double words 1 0 x x 32 double words 1 1 x x table 196. i port i/o enable, output clock and gated clock phase control; global set 87h[7:4] [1] output clock and gated clock phase control control bits 7 to 4 ipck3 [2] ipck2 [2] ipck1 ipck0 iclk default output phase x x 0 0 iclk phase shifted by 1 2 clock cycle t recommended for icks1 = 1 and icks0 = 0 (subaddress 80h) xx 01 iclk phase shifted by approximately 3 ns x x 1 0 iclk phase shifted by 1 2 clock cycle + approximately 3 ns t alternatively to setting 01 xx 11 idq = gated clock default output phase 0 0 x x idq = gated clock phase shifted by 1 2 clock cycle t recommended for gated clock output 01 xx idq = gated clock phase shifted by approximately 3ns 10 xx idq = gated clock phase shifted by 1 2 clock cycle + approximately 3 ns t alternatively to setting 01 11 xx table 197. i port i/o enable, output clock and gated clock phase control; global set 87h[1:0] i port i/o enable control bits 1 and 0 ipe1 ipe0 i port output is disabled by software 0 0 i port output is enabled by software 0 1 i port output is enabled by pin itri at logic 0 1 0 i port output is enabled by pin itri at logic 1 1 1
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 162 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.5.3 subaddress 88h [1] x = dont care. [2] bit swrst is now located here. [1] x = dont care. 11.2.5.4 subaddress 8fh table 198. power save control; global set 88h[7:4] [1] power save control control bits 7 to 4 ch4en ch2en swrst [2] dprog dprog = 0 after reset x x x 0 dprog = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit prdon; if dprog was set to logic 1 and prdon status bit shows a logic 0, a power-up or start-up fail has occurred xxx 1 scaler path is reset to its idle state, software reset x x 0 x scaler is switched back to operation x x 1 x ad1x analog channel is in power-down mode x 0 x x ad1x analog channel is active x 1 x x ad2x analog channel is in power-down mode 0 x x x ad2x analog channel is active 1 x x x table 199. power save control; global set 88h[3] and 88h[1:0] [1] power save control control bits 3, 1 and 0 slm3 slm1 slm0 decoder and vbi slicer are in operational mode x x 0 decoder and vbi slicer are in power-down mode; scaler only operates, if scaler input and iclk source is the x port (refer to subaddresses 80h and 91h/c1h) xx1 scaler is in operational mode x 0 x scaler is in power-down mode; scaler in power-down stops i port output x1 x audio clock generation active 0 x x audio clock generation in power-down and output disabled 1 x x table 200. status information scaler part; 8fh[7:0]; read only register bit i 2 c-bus status bit function [1] 7 xtri status on input pin xtri, if not used for 3-state control, usable as hardware ?ag for software use 6 itri status on input pin itri, if not used for 3-state control, usable as hardware ?ag for software use 5 ffil status of the internal fifo almost ?lled ?ag 4 ffov status of the internal fifo over?ow ?ag 3 prdon copy of bit dprog, can be used to detect power-up and start-up fails
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 163 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] status information is unsynchronized and shows the actual status at the time of i 2 c-bus read. 11.2.5.5 subaddresses 90h and c0h [1] x = dont care. [1] x = dont care. 2 errof error ?ag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate con?icts, e.g. if output data rate is much too low and all internal fifo capacity used 1 fidsci status of the ?eld sequence id at the scalers input 0 fidsco status of the ?eld sequence id at the scalers output, scaler processing dependent table 200. status information scaler part; 8fh[7:0]; read only register continued bit i 2 c-bus status bit function [1] table 201. task handling control; register set a [90h[7:6]] and b [c0h[7:6]] [1] event handler control control bits 7 and 6 conlh ofidc output ?eld id is ?eld id from scaler input x 0 output ?eld id is task status ?ag, which changes every time a selected task is activated (not synchronized to input ?eld id) x1 scaler sav/eav byte bit 7 and task ?ag = 1, default 0x scaler sav/eav byte bit 7 and task ?ag = 0 1 x table 202. task handling control; register set a [90h[5:3]] and b [c0h[5:3]] event handler control control bits 5 to 3 fskp2 fskp1 fskp0 active task is carried out directly 0 0 0 1 ?eld is skipped before active task is carried out 0 0 1 ... ?elds are skipped before active task is carried out ... ... ... 6 ?elds are skipped before active task is carried out 1 1 0 7 ?elds are skipped before active task is carried out 1 1 1 table 203. task handling control; register set a [90h[2:0]] and b [c0h[2:0]] [1] event handler control control bits 2 to 0 rptsk strc1 strc0 event handler triggers immediately after ?nishing a task x 0 0 event handler triggers with next v-sync x 0 1 event handler triggers with ?eld id = 0 x 1 0 event handler triggers with ?eld id = 1 x 1 1 if active task is ?nished, handling is taken over by the next task 0 x x active task is repeated once, before handling is taken over by the next task 1xx
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 164 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.5.6 subaddresses 91h to 93h [1] x = dont care. [1] x = dont care. [2] fsc2 and fsc1 only to be used if x port input source does not provide chroma information for every input line. x port input stream must contain dummy chroma bytes. table 204. x port formats and con?guration; register set a [91h[7:3]] and b [c1h[7:3]] [1] scaler input format and con?guration source selection control bits 7 to 3 conlv hldfv scsrc1 scsrc0 scrqe only if xrqt[83h[2]] = 1: scaler input source reacts on SAA7108AE; saa7109ae request xxxx0 scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1, if SAA7108AE; saa7109ae decoder part is source of scaler or xrqt[83h[2]] = 0) xxxx1 scaler input source is data from decoder, data type is provided according to t ab le 28 xx00x scaler input source is y-c b -c r data from x port xx01x scaler input source is raw digital cvbs from selected analog channel, for backward compatibility only, further use is not recommended xx10x scaler input source is raw digital cvbs (or 16-bit y + c b -c r , if no 16-bit outputs are active) from x port xx11x sav/eav code bits 6 and 5 (f and v) may change between sav and eav x0xxx sav/eav code bits 6 and 5 (f and v) are synchronized to scalers output line start x1xxx sav/eav code bit 5 (v) and v gate on pin igpv as generated by the internal processing; see figure 48 0xxxx sav/eav code bit 5 (v) and v gate are inverted 1xxxx table 205. x port formats and con?guration; register set a [91h[2:0]] and b [c1h[2:0]] [1] scaler input format and con?guration format control control bits 2 to 0 fsc2 [2] fsc1 [2] fsc0 input is y-c b -c r 4 : 2 : 2 like sampling scheme x x 0 input is y-c b -c r 4 : 1 : 1 like sampling scheme x x 1 chroma is provided every line, default 00x chroma is provided every 2nd line 0 1 x chroma is provided every 3rd line 1 0 x chroma is provided every 4th line 1 1 x
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 165 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. [1] x = dont care. table 206. x port input reference signal de?nitions; register set a [92h[7:4]] and b [c2h[7:4]] [1] x port input reference signal de?nitions control bits 7 to 4 xfdv xfdh xdv1 xdv0 rising edge of xrv input and decoder v123 is vertical reference xxx0 falling edge of xrv input and decoder v123 is vertical reference xxx1 xrv is a v-sync or v gate signal x x 0 x xrv is a frame sync, v pulses are generated internally on both edges of fs input xx1 x x port ?eld id is state of xrh at reference edge on xrv (de?ned by xfdv) x0 xx field id (decoder and x port ?eld id) is inverted x 1 x x reference edge for ?eld detection is falling edge of xrv 0 xxx reference edge for ?eld detection is rising edge of xrv 1 xxx table 207. x port input reference signal de?nitions; register set a [92h[3:0]] and b [c2h[3:0]] [1] x port input reference signal de?nitions control bits 3 to 0 xcode xdh xdq xcks xclk input clock and xdq input quali?er are needed xxx0 data rate is de?ned by xclk only, no xdq signal used xxx1 data are quali?ed at xdq input at logic 1 x x 0 x data are quali?ed at xdq input at logic 0 x x 1 x rising edge of xrh input is horizontal reference x 0 x x falling edge of xrh input is horizontal reference x 1 x x reference signals are taken from xrh and xrv 0 x x x reference signals are decoded from eav and sav 1 x x x
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 166 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. [1] x = dont care. table 208. i port output format and con?guration; register set a [93h[7:5]] and b [c3h[7:5]] [1] i port output format and con?guration control bits 7 to 5 icode i8_16 fysk all lines will be output x x 0 skip the number of leading y only lines, as de?ned by foi1 and foi0 x x 1 double words are transferred byte wise, see subaddress 85h bits iswp1 and iswp0 x0 x double words are transferred 16-bit word wise via ipd and hpd, see subaddress 85h bits iswp1 and iswp0 x1 x no itu 656 like sav/eav codes are available 0 x x itu 656 like sav/eav codes are inserted in the output data stream, framed by a quali?er 1xx table 209. i port output format and con?guration; register set a [93h[4:0]] and b [c3h[4:0]] [1] i port output format and con?guration control bits 4 to 0 foi1 foi0 fsi2 fsi1 fsi0 4 : 2 : 2 double word formatting x x 0 0 0 4 : 1 : 1 double word formatting x x 0 0 1 4 : 2 : 0, only every 2nd line y + c b -c r output, in between y only output xx010 4 : 1 : 0, only every 4th line y + c b -c r output, in between y only output xx011 y only x x 1 0 0 not de?ned x x 1 0 1 not de?ned x x 1 1 0 not de?ned x x 1 1 1 no leading y only line, before 1st y + c b -c r line is output 0 0 xxx 1 leading y only line, before 1st y + c b -c r line is output 0 1 xxx 2 leading y only lines, before 1st y + c b -c r line is output 1 0 xxx 3 leading y only lines, before 1st y + c b -c r line is output 1 1 xxx
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 167 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.5.7 subaddresses 94h to 9bh [1] reference for counting are luminance samples. [1] reference for counting are luminance samples. [1] for trigger condition: strc[1:0] 90h[1:0] = 00; yo + ys > (number of input lines per ?eld - 2), will result in ?eld dropping. other trigger conditions: yo > (number of input lines per ?eld - 2), will result in ?eld dropping. table 210. horizontal input window start; register set a [94h[7:0]; 95h[3:0]] and b [c4h[7:0]; c5h[3:0]] horizontal input acquisition window de?nition offset in x (horizontal) direction [1] control bits a [95h[3:0]] and b [c5h[3:0]] a [94h[7:0]] and b [c4h[7:0]] xo11 xo10 xo9 xo8 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 a minimum of 2 should be kept, due to a line counting mismatch 00000 0000010 odd offsets are changing the c b -c r sequence in the output stream to c r -c b sequence 00000 0000011 maximum possible pixel offset = 4095 11111 1111111 table 211. horizontal input window length; register set a [96h[7:0]; 97h[3:0]] and b [c6h[7:0]; c7h[3:0]] horizontal input acquisition window de?nition input window length in x (horizontal) direction [1] control bits a [97h[3:0]] and b [c7h[3:0]] a [96h[7:0]] and b [c6h[7:0]] xs11 xs10 xs9 xs8 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 no output 00000 0000000 odd lengths are allowed, but will be rounded up to even lengths 00000 0000001 maximum possible number of input pixels = 4095 11111 1111111 table 212. vertical input window start; register set a [98h[7:0]; 99h[3:0]] and b [c8h[7:0]; c9h[3:0]] vertical input acquisition window de?nition offset in y (vertical) direction [1] control bits a [99h[3:0]] and b [c9h[3:0]] a [98h[7:0]] and b [c8h[7:0]] yo11 yo10 yo9 yo8 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 line offset = 0 00000 0000000 line offset = 1 00000 0000001 maximum line offset = 4095 11111 1111111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 168 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] for trigger condition: strc[1:0] 90h[1:0] = 00; yo + ys > (number of input lines per ?eld - 2), will result in ?eld dropping. other trigger conditions: ys > (number of input lines per ?eld - 2), will result in ?eld dropping. 11.2.5.8 subaddresses 9ch to 9fh [1] reference for counting are luminance samples. [2] if the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. [1] if the desired output length is greater than the number of scaled output lines, the processing is cut. table 213. vertical input window length; register set a [9ah[7:0]; 9bh[3:0]] and b [cah[7:0]; cbh[3:0]] vertical input acquisition window de?nition input window length in y (vertical) direction [1] control bits a [9bh[3:0]] and b [cbh[3:0]] a [9ah[7:0]] and b [cah[7:0]] ys11 ys10 ys9 ys8 ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 no input lines 00000 0000000 1 input line 00000 0000001 maximum possible number of input lines = 4095 11111 1111111 table 214. horizontal output window length; register set a [9ch[7:0]; 9dh[3:0]] and b [cch[7:0]; cdh[3:0]] horizontal output acquisition window de?nition number of desired output pixels in x (horizontal) direction [1] control bits a [9dh[3:0]] and b [cdh[3:0]] a [9ch[7:0]] and b [cch[7:0]] xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 no output 00000 0000000 odd lengths are allowed, but will be ?lled up to even lengths 00000 0000001 maximum possible number of input pixels = 4095 [2] 11111 1111111 table 215. vertical output window length; register set a [9eh[7:0]; 9fh[3:0]] and b [ceh[7:0]; cfh[3:0]] vertical output acquisition window de?nition number of desired output lines in y (vertical) direction control bits a [9fh[3:0]] and b [cfh[3:0]] a [9eh[7:0]] and b [ceh[7:0]] yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 no output 00000 0000000 1pixel 00000 0000001 maximum possible number of output lines = 4095 [1] 11111 1111111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 169 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.5.9 subaddresses a0h to a2h [1] x = dont care. table 216. horizontal prescaling; register set a [a0h[5:0]] and b [d0h[5:0]] horizontal integer prescaling ratio (xpsc) control bits 5 to 0 xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 not allowed 0 0 0 0 0 0 downscale = 1 0 0 0 0 0 1 downscale = 1 2 000010 ... ... ... ... ... ... ... downscale = 1 63 111111 table 217. accumulation length; register set a [a1h[5:0]] and b [d1h[5:0]] horizontal prescaler accumulation sequence length (xacl) control bits 5 to 0 xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 accumulation length = 1 0 0 0 0 0 0 accumulation length = 2 0 0 0 0 0 1 ... ... ... ... ... ... ... accumulation length = 64 1 1 1 1 1 1 table 218. prescaler dc gain and fir pre?lter control; register set a [a2h[7:4]] and b [d2h[7:4]] [1] fir pre?lter control control bits 7 to 4 pfuv1 pfuv0 pfy1 pfy0 luminance fir ?lter bypassed x x 0 0 h_y(z) = 1 4 (1 2 1) x x 0 1 h_y(z) = 1 8 ( - 1 1 1.75 4.5 1.75 1 - 1) x x 1 0 h_y(z) = 1 8 (12221) x x 1 1 chrominance fir ?lter bypassed 0 0 x x h_uv(z) = 1 4 (121) 0 1 x x h_uv(z) = 1 32 (381083) 1 0 x x h_uv(z) = 1 8 (12221) 1 1 x x table 219. prescaler dc gain and fir pre?lter control; register set a [a2h[3:0]] and b [d2h[3:0]] [1] prescaler dc gain control bits 3 to 0 xc2_1 xdcg2 xdcg1 xdcg0 prescaler output is renormalized by gain factor = 1 x 0 0 0 prescaler output is renormalized by gain factor = 1 2 x001 prescaler output is renormalized by gain factor = 1 4 x010 prescaler output is renormalized by gain factor = 1 8 x011 prescaler output is renormalized by gain factor = 1 16 x100 prescaler output is renormalized by gain factor = 1 32 x101 prescaler output is renormalized by gain factor = 1 64 x110
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 170 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] x = dont care. 11.2.5.10 subaddresses a4h to a6h prescaler output is renormalized by gain factor = 1 128 x111 weighting of all accumulated samples is factor 1; e.g. xacl = 4 t sequence 1 + 1 + 1 + 1 + 1 0xxx weighting of samples inside sequence is factor 2; e.g. xacl = 4 t sequence 1 + 2 + 2 + 2 + 1 1xxx table 219. prescaler dc gain and fir pre?lter control; register set a [a2h[3:0]] and b [d2h[3:0]] [1] continued prescaler dc gain control bits 3 to 0 xc2_1 xdcg2 xdcg1 xdcg0 table 220. luminance brightness control; register set a [a4h[7:0]] and b [d4h[7:0]] luminance brightness control control bits 7 to 0 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 value=0 00000000 nominal value = 128 1 0 0 0 0 0 0 0 value = 255 1 1 1 1 1 1 1 1 table 221. luminance contrast control; register set a [a5h[7:0]] and b [d5h[7:0]] luminance contrast control control bits 7 to 0 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 gain=0 00000000 gain = 1 64 00000001 nominal gain = 64 0 1 0 0 0 0 0 0 gain = 127 64 01111111 table 222. chrominance saturation control; register set a [a6h[7:0]] and b [d6h[7:0]] chrominance saturation control control bits 7 to 0 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 gain=0 00000000 gain = 1 64 00000001 nominal gain = 64 0 1 0 0 0 0 0 0 gain = 127 64 01111111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 171 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.5.11 subaddresses a8h to aeh [1] bits xscy[15:13] are reserved and are set to logic 0. [1] bits xscc[15:13] are reserved and are set to logic 0. table 223. horizontal luminance scaling increment; register set a [a8h[7:0]; a9h[7:0]] and b [d8h[7:0]; d9h[7:0]] horizontal luminance scaling increment control bits a [a9h[7:4]] b [d9h[7:4]] a [a9h[3:0]] b [d9h[3:0]] a [a8h[7:4]] b [d8h[7:4]] a [a8h[3:0]] b [d8h[3:0]] xscy[15:12] [1] xscy[11:8] xscy[7:4] xscy[3:0] scale = 1024 1 (theoretical) zoom 0000 0000 0000 0000 scale = 1024 294 , lower limit de?ned by data path structure 0000 0001 0010 0110 scale = 1024 1023 zoom 0000 0011 1111 1111 scale = 1, equals 1024 0000 0100 0000 0000 scale = 1024 1025 downscale 0000 0100 0000 0001 scale = 1024 8191 downscale 0001 1111 1111 1111 table 224. horizontal luminance phase offset; register set a [aah[7:0]] and b [dah[7:0]] horizontal luminance phase offset control bits 7 to 0 xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 offset = 0 0 0 0 0 0 0 0 0 offset = 1 32 pixel00000001 offset = 32 32 =1pixel00100000 offset = 255 32 pixel11111111 table 225. horizontal chrominance scaling increment; register set a [ach[7:0]; adh[7:0]] and b [dch[7:0]; ddh[7:0]] horizontal chrominance scaling increment control bits a [adh[7:4]] b [ddh[7:4]] a [adh[3:0]] b [ddh[3:0]] a [ach[7:4]] b [dch[7:4]] a [ach[3:0]] b [dch[3:0]] xscc[15:12] [1] xscc[11:8] xscc[7:4] xscc[3:0] this value must be set to the luminance value 1 2 xscy[15:0] 0000 0000 0000 0000 0000 0000 0000 0001 0001 1111 1111 1111 table 226. horizontal chrominance phase offset; register set a [aeh[7:0]] and b [deh[7:0]] horizontal chrominance phase offset control bits 7 to 0 xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 this value must be set to 1 2 xphy[7:0] 00000000 00000001 11111111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 172 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 11.2.5.12 subaddresses b0h to bfh [1] x = dont care. table 227. vertical luminance scaling increment; register set a [b0h[7:0]; b1h[7:0]] and b [e0h[7:0]; e1h[7:0]] vertical luminance scaling increment control bits a [b1h[7:4]] b [e1h[7:4]] a [b1h[3:0]] b [e1h[3:0]] a [b0h[7:4]] b [e0h[7:4]] a [b0h[3:0]] b [e0h[3:0]] yscy[15:12] yscy[11:8] yscy[7:4] yscy[3:0] scale = 1024 1 (theoretical) zoom 0000 0000 0000 0001 scale = 1024 1023 zoom 0000 0011 1111 1111 scale = 1, equals 1024 0000 0100 0000 0000 scale = 1024 1025 downscale 0000 0100 0000 0001 scale = 1 63.999 downscale 1111 1111 1111 1111 table 228. vertical chrominance scaling increment; register set a [b2h[7:0]; b3h[7:0]] and b [e2h[7:0]; e3h[7:0]] vertical chrominance scaling increment control bits a [b3h[7:4]] b [e3h[7:4]] a [b3h[3:0]] b [e3h[3:0]] a [b2h[7:4]] b [e2h[7:4]] a [b2h[3:0]] b [e2h[3:0]] yscc[15:12] yscc[11:8] yscc[7:4] yscc[3:0] this value must be set to the luminance value yscy[15:0] 0000 0000 0000 0001 1111 1111 1111 1111 table 229. vertical scaling mode control; register set a [b4h[4 and 0]] and b [e4h[4 and 0]] [1] vertical scaling mode control control bits 4 and 0 ymir ymode vertical scaling performs linear interpolation between lines x 0 vertical scaling performs higher order accumulating interpolation, better alias suppression x1 no mirroring 0 x lines are mirrored 1 x table 230. vertical chrominance phase offset 00; register set a [b8h[7:0]] and b [e8h[7:0]] vertical chrominance phase offset control bits 7 to 0 ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 offset = 0 00000000 offset = 32 32 = 1 line 00100000 offset = 255 32 lines 11111111
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 173 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 12. programming start setup of digital video decoder part 12.1 decoder part the given values force the following behavior of the SAA7108AE; saa7109ae decoder part: ? the analog input ai11 expects an ntsc m, pal b, d, g, h and i or secam signal in cvbs format; analog anti-alias ?lter and agc active ? automatic ?eld detection enabled ? standard itu 656 output format enabled on expansion (x) port ? contrast, brightness and saturation control in accordance with itu standards ? adaptive comb ?lter for luminance and chrominance activated ? pins llc, llc2, xtoutd, rts0, rts1 and rtco are set to 3-state table 231. vertical luminance phase offset 00; register set a [bch[7:0]] and b [ech[7:0]] vertical luminance phase offset control bits 7 to 0 ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 offset = 0 00000000 offset = 32 32 = 1 line 00100000 offset = 255 32 lines 11111111 table 232. decoder part start setup values for the three main standards subaddress (hexadecimal) register function bit name [1] values (hexadecimal) ntsc m pal b, d, g, h and i secam 00 chip version id7 to id4 read only 01 increment delay x, x, x, x, idel3 to idel0 08 08 08 02 analog input control 1 fuse1, fuse0, gudl1, gudl0 and mode3 to mode0 c0 c0 c0 03 analog input control 2 x, hlnrs, vbsl, wpoff, holdg, gafix, gai28 and gai18 10 10 10 04 analog input control 3 gai17 to gai10 90 90 90 05 analog input control 4 gai27 to gai20 90 90 90 06 horizontal sync start hsb7 to hsb0 eb eb eb 07 horizontal sync stop hss7 to hss0 e0 e0 e0 08 sync control aufd, fsel, foet, htc1, htc0, hpll, vnoi1 and vnoi0 98 98 98 09 luminance control byps, ycomb, ldel, lubw and lufi3 to lufi0 40 40 1b 0a luminance brightness control dbri7 to dbri0 80 80 80 0b luminance contrast control dcon7 to dcon0 44 44 44 0c chrominance saturation control dsat7 to dsat0 40 40 40 0d chrominance hue control huec7 to huec0 00 00 00 0e chrominance control 1 cdto, cstd2 to cstd0, dcvf, fctc, x and ccomb 89 81 d0
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 174 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] all x values must be set to logic 0. 12.2 audio clock generation part the given values force the following behavior of the SAA7108AE; saa7109ae audio clock generation part: ? used crystal is 24.576 mhz ? expected ?eld frequency is 59.94 hz (e.g. ntsc m standard) ? generated audio master clock frequency at pin amclk is 256 khz 44.1 khz = 11.2896 mhz ? amclk is externally connected to amxclk (short-cut between pins k12 and j12) ? asclk = 32 khz 44.1 khz = 1.4112 mhz ? alrclk is 44.1 khz 0f chrominance gain control acgc and cgain6 to cgain0 2a 2a 80 10 chrominance control 2 offu1, offu0, offv1, offv0, chbw and lcbw2 to lcbw0 0e 06 00 11 mode/delay control colo, rtp1, hdel1, hdel0, rtp0 and ydel2 to ydel0 00 00 00 12 rt signal control rtse13 to rtse10 and rtse03 to rtse00 00 00 00 13 rt/x port output control rtce, xrhs, xrvs1, xrvs0, hlsel and ofts2 to ofts0 00 00 00 14 analog/adc/compatibility control cm99, uptcv, aosl1, aosl0, xtoute, oldsb, apck1 and apck0 00 00 00 15 vgate start, fid change vsta7 to vsta0 11 11 11 16 vgate stop vsto7 to vsto0 fe fe fe 17 miscellaneous, vgate con?guration and msbs llce, llc2e, x, x, x, vgps, vsto8 and vsta8 40 40 40 18 raw data gain control rawg7 to rawg0 40 40 40 19 raw data offset control rawo7 to rawo0 80 80 80 1a to 1e reserved x, x, x, x, x, x, x, x 00 00 00 1f status byte video decoder (oldsb = 0) intl, hlvln, fidt, glimt, glimb, wipa, copro and rdcap read only table 232. decoder part start setup values for the three main standards continued subaddress (hexadecimal) register function bit name [1] values (hexadecimal) ntsc m pal b, d, g, h and i secam
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 175 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] all x values must be set to logic 0. 12.3 data slicer and data type control part the given values force the following behavior of the SAA7108AE; saa7109ae vbi data slicer part: ? closed captioning data are expected at line 21 of ?eld 1 (60 hz/525 line system) ? all other lines are processed as active video ? sliced data are framed by itu 656 like sav/eav sequence (did[5:0] = 3eh t msb of sav/eav = 1) table 233. audio clock part setup values subaddress (hexadecimal) register function bit name [1] values (binary) start (hexadecimal) 7 6 5 4 3 2 1 0 30 audio master clock cycles per ?eld; bits 7 to 0 acpf7 to acpf0 10111100bc 31 audio master clock cycles per ?eld; bits 15 to 8 acpf15 to acpf8 11011111df 32 audio master clock cycles per ?eld; bits 17 and 16 x, x, x, x, x, x, acpf17 and acpf16 0000001002 33 reserved x, x, x, x, x, x, x, x 0000000000 34 audio master clock nominal increment; bits 7 to 0 acni7 to acni0 11001101cd 35 audio master clock nominal increment; bits 15 to 8 acni15 to acni8 11001100cc 36 audio master clock nominal increment; bits 21 to 16 x, x, acni21 to acni16 001110103a 37 reserved x, x, x, x, x, x, x, x 0000000000 38 clock ratio amxclk to asclk x, x, sdiv5 to sdiv0 0000001103 39 clock ratio asclk to alrclk x, x, lrdiv5 to lrdiv0 0001000010 3a audio clock generator basic setup x, x, x, x, apll, amvr, lrph, scph 0000000000 3b to 3f reserved x, x, x, x, x, x, x, x 0000000000 table 234. data slicer start setup values subaddress (hexadecimal) register function bit name [1] values (binary) start (hexadecimal) 7 6 5 4 3 2 1 0 40 slicer control 1 x, ham_n, fce, hunt_n, x, x, x, x 0100000040 41 to 53 line control register 2 to 20 lcrn_7 to lcrn_0 (n = 2 to 20) 11111111ff 54 line control register 21 lcr21_7 to lcr21_0 010111115f 55 to 57 line control register lcrn_7 to lcrn_0 (n=22to24) 11111111ff 58 programmable framing code fc7 to fc0 0000000000 59 horizontal offset for slicer hoff7 to hoff0 0100011147 5a vertical offset for slicer voff7 to voff0 0000011006 [2]
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 176 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] all x values must be set to logic 0. [2] changes for 50 hz/625 line systems: subaddress 5ah = 03h and subaddress 5bh = 03h. 12.4 scaler and interfaces t ab le 235 shows some examples for the scaler programming with: ? prsc = prescale ratio ? ?sc = ?ne scale ratio ? vsc = vertical scale ratio the ratio is de?ned as: in the following settings the vbi data slicer is inactive. to activate the vbi data slicer, vitx[1:0] 86h[7:6] has to be set to 11. depending on the vbi data slicer settings, the sliced vbi data is inserted after the end of the scaled video lines, if the regions of vbi data slicer and scaler overlaps. to compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 lines to 290 lines, respectively 242 lines for xs, but the scaler increment calculations are done with 288 lines, respectively 240 lines. 5b ?eld offset and msbs for horizontal and vertical offset foff, recode, x, voff8, x, hoff10 to hoff8 1000001183 [2] 5c reserved x, x, x, x, x, x, x, x 0000000000 5d header and data identi?cation code control fvref, x, did5 to did0 001111103e 5e sliced data identi?cation code x, x, sdid5 to sdid0 0000000000 5f reserved x, x, x, x, x, x, x, x 0000000000 60 slicer status byte 0 -, fc8v, fc7v, vpsv, ppv, ccv, -, - read only register 61 slicer status byte 1 -, -, f21_n, ln8 to ln4 read only register 62 slicer status byte 2 ln3 to ln0, dt3 to dt0 read only register table 234. data slicer start setup values continued subaddress (hexadecimal) register function bit name [1] values (binary) start (hexadecimal) 7 6 5 4 3 2 1 0 number of input pixel number of output pixel ---------------------------------------------------------------
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 177 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 12.4.1 trigger condition for trigger condition strc[1:0] 90h[1:0] not equal 00. if the value of (yo + ys) is greater than or equal to 262 (ntsc), respectively 312 (pal) the output ?eld rate is reduced to 30 hz, respectively 25 hz. horizontal and vertical offsets (xo and yo) have to be used to adjust the displayed video in the display window. as this adjustment is application dependent, the listed values are only dummy values. 12.4.2 maximum zoom factor the maximum zoom factor is dependent on the back-end data rate and therefore back-end clock and data format dependent (8-bit or 16-bit output). the maximum horizontal zoom is limited to approximately 3.5, due to internal data path restrictions. 12.4.3 examples table 235. example of con?gurations see settings in t ab le 236 . example number scaler source and reference events input window output window scale ratios 1 analog input to 8-bit i port output, with sav/eav codes, 8-bit serial byte stream decoder output at x port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; h and v gates on igph and igpv, igp0 = vbi sliced data ?ag, igp1 = fifo almost full, level 3 24, idq quali?er logic 1 active 720 240 720 240 prsc = 1; ?sc = 1; vsc = 1 2 analog input to 16-bit output, without sav/eav codes, y on i port, c b -c r on h port and decoder output at x port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; h and v pulses on igph and igpv, output fid on igp0, igp1 ?xed to logic 1, idq quali?er logic 0 active 704 288 768 288 prsc = 1; ?sc = 0.91667; vsc=1 3 x port input 8 bit with sav/eav codes, no reference signals on xrh and xrv, xclk as gated clock; ?eld detection and acquisition trigger on different events; acquisition triggers at rising edge vertical and rising edge horizontal reference signal; i port output 8-bit with sav/eav codes like example number 1 720 240 352 288 prsc = 2; ?sc = 1.022; vsc = 0.8333 4 x port and h port for 16-bit y-c b -c r 4:2:2 input (if no 16-bit output selected); xrh and xrv as references; ?eld detection and acquisition trigger at falling edge vertical and rising edge horizontal reference signal; i port output 8-bit with sav/eav codes, but y only output 720 288 200 80 prsc = 2; ?sc = 1.8; vsc = 3.6
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 178 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 236. scaler and interface con?guration example i 2 c-bus address (hex) main functionality example 1 example 2 example 3 example 4 hex dec hex dec hex dec hex dec global settings 80 task enable, idq and back-end clock de?nition 10 - 10 - 10 - 10 - 83 xclk output phase and x port output enable 01 - 01 - 00 - 00 - 84 igph, igpv, igp0 and igp1 output de?nition a0 - c5 - a0 - a0 - 85 signal polarity control and i port byte swapping 10 - 09 - 10 - 10 - 86 fifo ?ag thresholds and video/text arbitration 45 - 40 - 45 - 45 - 87 iclk and idq output phase and i port enable 01 - 01 - 01 - 01 - 88 power save control and software reset f0 - f0 - f0 - f0 - task a: scaler input con?guration and output format settings 90 task handling 00 - 00 - 00 - 00 - 91 scaler input source and format de?nition 08 - 08 - 18 - 38 - 92 reference signal de?nition at scaler input 10 - 10 - 10 - 10 - 93 i port output formats and con?guration 80 - 40 - 80 - 84 - input and output window de?nition 94 horizontal input offset (xo) 10 16 10 16 10 16 10 16 95 00 - 00 - 00 - 00 - 96 horizontal input (source) window length (xs) d0 720 c0 704 d0 720 d0 720 97 02 - 02 - 02 - 02 - 98 vertical input offset (yo) 0a 10 0a 10 0a 10 0a 10 99 00 - 00 - 00 - 00 - 9a vertical input (source) window length (ys) f2 242 22 290 f2 242 22 290 9b 00 - 01 - 00 - 01 - 9c horizontal output (destination) window length (xd) d0 720 00 768 60 352 c8 200 9d 02 - 03 - 01 - 00 - 9e vertical output (destination) window length (yd) f0 240 20 288 20 288 50 80 9f 00 - 01 - 01 - 00 - pre?ltering and prescaling a0 integer prescale (value 00 not allowed) 01 - 01 - 02 - 02 - a1 accumulation length for prescaler 00 - 00 - 02 - 03 - a2 fir pre?lter and prescaler dc normalization 00 - 00 - aa - f2 -
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 179 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec a4 scaler brightness control 80 128 80 128 80 128 80 128 a5 scaler contrast control 40 64 40 64 40 64 11 17 a6 scaler saturation control 40 64 40 64 40 64 11 17 horizontal phase scaling a8 horizontal scaling increment for luminance 00 1024 aa 938 18 1048 34 1844 a9 04 - 03 - 04 - 07 - aa horizontal phase offset luminance 00 - 00 - 00 - 00 - ac horizontal scaling increment for chrominance 00 512 d5 469 0c 524 9a 922 ad 02 - 01 - 02 - 03 - ae horizontal phase offset chrominance 00 - 00 - 00 - 00 - vertical scaling b0 vertical scaling increment for luminance 00 1024 00 1024 55 853 66 3686 b1 04 - 04 - 03 - 0e - b2 vertical scaling increment for chrominance 00 1024 00 1024 55 853 66 3686 b3 04 - 04 - 03 - 0e - b4 vertical scaling mode control 00 - 00 - 00 - 01 - b8 to bf vertical phase offsets luminance and chrominance (need to be used for interlace correct scaled output) start with b8h to bfh at 00h, if there are no problems with the interlaced scaled output optimize according to section 9.3.3.2 table 236. scaler and interface con?guration example continued i 2 c-bus address (hex) main functionality example 1 example 2 example 3 example 4 hex dec hex dec hex dec hex dec
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 180 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 13. limiting values [1] condition for maximum voltage at digital inputs or i/o pins: 3.0 v < v ddd < 3.6 v. [2] class 2 according to jesd22-a114d. [3] class a according to eia/jesd22-a115-a. 14. thermal characteristics [1] the overall r th(j-a) value can vary depending on the board layout. to minimize the effective r th(j-a) all power and ground pins must be connected to the power and ground layers directly. an ample copper area directly under the SAA7108AE; saa7109ae with a number of through-hole plating, connected to the ground layer (four-layer board: second layer), can also reduce the effective r th(j-a) . please do not use any solder-stop varnish under the chip. in addition the usage of soldering glue with a high thermal conductance after curing is recommended. table 237. limiting values in accordance with the absolute maximum rating system (iec 60134). all ground pins connected together and grounded (0 v); all supply pins connected together. symbol parameter conditions min max unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v i(a) input voltage at analog inputs - 0.5 +4.6 v v i(n) input voltage at pins xtali, sda and scl - 0.5 v ddd + 0.5 v v i(d) input voltage at digital inputs or i/o pins outputs in 3-state - 0.5 +4.6 v outputs in 3-state [1] - 0.5 +5.5 v d v ss voltage difference between v ssa(n) and v sse(n) or v ssi(n) - 100 mv t stg storage temperature - 65 +150 c t amb ambient temperature 0 70 c v esd electrostatic discharge voltage human body model [2] - 2000 v machine model [3] - 150 v table 238. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 32 [1] k/w
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 181 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 15. characteristics table 239. characteristics of the digital video encoder part t amb =0 c to 70 c (typical values measured at t amb =25 c); unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dda analog supply voltage 3.15 3.3 3.45 v v ddie digital supply voltage 3.15 3.3 3.45 v v dd(dvo) digital supply voltage (dvo) 1.045 1.1 1.155 v 1.425 1.5 1.575 v 1.71 1.8 1.89 v 2.375 2.5 2.625 v 3.135 3.3 3.465 v i dda analog supply current [1] 1 110 115 ma i ddd digital supply current [2] 1 175 200 ma inputs v il low-level input voltage v dd(dvo) = 1.1 v, 1.5 v, 1.8 v or 2.5 v [3] - 0.1 - +0.2 v v dd(dvo) = 3.3 v [3] - 0.5 - +0.8 v pins rese, tmse, tcke, trst e and tdie - 0.5 - +0.8 v v ih high-level input voltage v dd(dvo) = 1.1 v, 1.5 v, 1.8 v or 2.5 v [3] v dd(dvo) - 0.2 - v dd(dvo) + 0.1 v v dd(dvo) = 3.3 v [3] 2-v dd(dvo) + 0.3 v pins rese, tmse, tcke, trst e and tdie 2-v ddie + 0.3 v i li input leakage current - - 10 m a c i input capacitance clocks - - 10 pf data - - 10 pf i/os at high-impedance - - 10 pf outputs v ol low-level output voltage v dd(dvo) = 1.1 v, 1.5 v, 1.8 v or 2.5 v [3] 0 - 0.1 v v dd(dvo) = 3.3 v [3] 0 - 0.4 v pins tdoe, ttxrq_xclko2, vsm and hsm_csync 0 - 0.4 v v oh high-level output voltage v dd(dvo) = 1.1 v, 1.5 v, 1.8 v or 2.5 v [3] v dd(dvo) - 0.1 - v dd(dvo) v v dd(dvo) = 3.3 v [3] 2.4 - v dd(dvo) v pins tdoe, ttxrq_xclko2, vsm and hsm_csync 2.4 - v ddie v
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 182 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec i 2 c-bus; pins sdae and scle v il low-level input voltage - 0.5 - +0.3v ddie v v ih high-level input voltage 0.7v ddie -v ddie + 0.3 v i i input current v i = low or high - 10 - +10 m a v ol low-level output voltage (pin sdae) i ol = 3 ma - - 0.4 v i o output current during acknowledge 3 - - ma clock timing; pins pixclki and pixclko t pixclk cycle time [4] 12 - - ns t d(clkd) delay from pixclko to pixclki [5] ---ns d duty factor t high /t pixclk [4] 40 50 60 % t high /t clko2 ; output 40 50 60 % t r rise time [4] - - 1.5 ns t f fall time [4] - - 1.5 ns input timing t su;dat input data set-up time pins pd11 to pd0 2 - - ns pins hsvgc, vsvgc and fsvgc [6] 2-- ns t hd;dat input data hold time pins pd11 to pd0 0.9 - - ns pins hsvgc, vsvgc and fsvgc [6] 1.5 - - ns crystal oscillator f nom nominal frequency - 27 - mhz d f/f nom permissible deviation of nominal frequency [7] - 50 10 - 6 - +50 10 - 6 crystal speci?cation t amb ambient temperature 0 - 70 c c l load capacitance 8 - - pf r s series resistance - - 80 w c 1 motional capacitance (typical) 1.2 1.5 1.8 ff c 0 parallel capacitance (typical) 2.8 3.5 4.2 pf data and reference signal output timing c o(l) output load capacitance 8 - 40 pf t o(h)(gfx) output hold time to graphics controller pins hsvgc, vsvgc, fsvgc and cbo 1.5 - - ns t o(d)(gfx) output delay time to graphics controller pins hsvgc, vsvgc, fsvgc and cbo - - 10 ns table 239. characteristics of the digital video encoder part continued t amb =0 c to 70 c (typical values measured at t amb =25 c); unless otherwise speci?ed. symbol parameter conditions min typ max unit
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 183 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] minimum value for i 2 c-bus bit downa = 1. [2] minimum value for i 2 c-bus bit downd = 1. [3] levels refer to pins pd11 to pd0, fsvgc, pixclki, vsvgc, pixclko, cbo, tvd, and hsvgc, being inputs or outputs directly connected to a graphics controller. input sensitivity is 1 2 v dd(dvo) + 100 mv for high and 1 2 v dd(dvo) - 100 mv for low. the reference voltage 1 2 v dd(dvo) is generated on chip. [4] the data is for both input and output direction. [5] this parameter is arbitrary, if pixclki is looped through the vgc. [6] tested with programming ifbp = 1. [7] if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/?eld frequency. [8] with r o(l) = 37.5 w and c ext = 20 pf (typical). t o(h) output hold time pins tdoe, ttxrq_xclko2, vsm and hsm_csync 3-- ns t o(d) output delay time pins tdoe, ttxrq_xclko2, vsm and hsm_csync - - 25 ns cvbs and rgb outputs v o(cvbs)(p-p) output voltage cvbs (peak-to-peak value) see t ab le 241 - 1.23 - v v o(vbs)(p-p) output voltage vbs (s-video) (peak-to-peak value) see t ab le 241 -1-v v o(c)(p-p) output voltage c (s-video) (peak-to-peak value) see t ab le 241 - 0.89 - v v o(rgb)(p-p) output voltage r, g, b (peak-to-peak value) see t ab le 241 - 0.7 - v d v o inequality of output signal voltages -2-% r o(l) output load resistance - 37.5 - w b dac output signal bandwidth of dacs - 3db [8] - 170 - mhz ile lf(dac) low frequency integral linearity error of dacs -- 3 lsb dle lf(dac) low frequency differential linearity error of dacs -- 1 lsb table 239. characteristics of the digital video encoder part continued t amb =0 c to 70 c (typical values measured at t amb =25 c); unless otherwise speci?ed. symbol parameter conditions min typ max unit b 3db C 1 2 p r ol () c ext 5pf + () () ----------------------------------------------------------- - =
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 184 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec table 240. characteristics of the digital video decoder part v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =0 c to 70 c (typical values measured at t amb =25 c); timings and levels refer to drawings and conditions illustrated in figure 67 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v ddd digital supply voltage 3.15 3.3 3.45 v i ddd digital supply current x port 3-state; 8-bit i port - 90 - ma p d power dissipation digital part - 300 - mw v dda analog supply voltage 3.15 3.3 3.45 v i dda analog supply current aosl1 and aosl0 = 0 cvbs mode - 47 - ma y/c mode - 72 - ma p a power dissipation analog part cvbs mode - 150 - mw y/c mode - 240 - mw p tot(a+d) total power dissipation analog and digital part cvbs mode [1] - 450 - mw y/c mode [1] - 540 - mw p tot(a+d)(pd) total power dissipation analog and digital part in power-down mode ce pulled down to ground - 5 - mw p tot(a+d)(ps) total power dissipation analog and digital part in power-save mode i 2 c-bus controlled via address 88h = 0fh -75-mw analog part i clamp clamping current v i = 0.9 v dc - 8- m a v i(p-p) input voltage (peak-to-peak value) for normal video levels 1 v (p-p), - 3db termination 27/47 w and ac coupling required; coupling capacitor = 22 nf - 0.7 - v ? z i ? input impedance clamping current off 200 - - k w c i input capacitance - - 10 pf a cs channel crosstalk f i < 5 mhz - - - 50 db 9-bit analog-to-digital converters b analog bandwidth at - 3 db - 7 - mhz f diff differential phase ampli?er plus anti-alias ?lter bypassed -2-deg g diff differential gain ampli?er plus anti-alias ?lter bypassed -2-% f clk(adc) adc clock frequency 12.8 - 14.3 mhz le dc(d) dc differential linearity error - 0.7 - lsb le dc(i) dc integral linearity error - 1 - lsb
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 185 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec digital inputs v il(sdad,scld) low-level input voltage pins sdad and scld - 0.5 - +0.3v ddd v v ih(sdad,scld) high-level input voltage pins sdad and scld 0.7v ddd -v ddd + 0.5 v v il(xtalid) low-level cmos input voltage pin xtalid - 0.3 - +0.8 v v ih(xtalid) high-level cmos input voltage pin xtalid 2.0 - v ddd + 0.3 v v il(n) low-level input voltage all other inputs - 0.3 - +0.8 v v ih(n) high-level input voltage all other inputs 2.0 - 5.5 v i li input leakage current - - 1 m a i li/o i/o leakage current - - 10 m a c i input capacitance i/o at high-impedance - - 8 pf digital outputs [2] v ol(sdad) low-level output voltage pin sdad sdad at 3 ma sink current - - 0.4 v v ol(clk) low-level output voltage for clocks 0 - 0.6 v v oh(clk) high-level output voltage for clocks 2.4 - v ddd + 0.5 v v ol(n) low-level output voltage all other digital outputs 0 - 0.4 v v oh(n) high-level output voltage all other digital outputs 2.4 - v ddd + 0.5 v clock output timing (llc and llc2) [3] c l output load capacitance 15 - 50 pf t cy cycle time pin llc 35 - 39 ns pin llc2 70 - 78 ns d duty factor for t llch /t llc and t llc2h /t llc2 c l =40pf 40 - 60 % t r rise time llc and llc2 0.2 v to v ddd - 0.2 v - - 5 ns t f fall time llc and llc2 v ddd - 0.2 v to 0.2 v - - 5 ns t d(llc-llc2) delay time between llc and llc2 output measured at 1.5 v; c l =25pf - 4 - +8 ns horizontal pll f hor(nom) nominal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f hor /f hor(nom) permissible static deviation - - 5.7 % table 240. characteristics of the digital video decoder part continued v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =0 c to 70 c (typical values measured at t amb =25 c); timings and levels refer to drawings and conditions illustrated in figure 67 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 186 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec subcarrier pll f sc(nom) nominal subcarrier frequency pal bghi - 4433619 - hz ntsc m - 3579545 - hz pal m - 3575612 - hz pal n - 3582056 - hz d f sc lock-in range 400 - - hz crystal oscillator for 32.11 mhz [4] f xtal(nom) nominal crystal frequency 3rd harmonic - 32.11 - mhz d f/f xtal(nom) nominal crystal frequency deviation - 70 10 - 6 - +70 10 - 6 d f/f xtal(nom)(t) nominal crystal frequency deviation with temperature - 30 10 - 6 - +30 10 - 6 crystal speci?cation (x1) t amb(x1) ambient temperature 0 - 70 c c l load capacitance 8 - - pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20 % - ff c 0 parallel capacitance - 4.3 20 % - pf crystal oscillator for 24.576 mhz [4] f xtal(nom) nominal crystal frequency 3rd harmonic - 24.576 - mhz d f/f xtal(nom) nominal crystal frequency deviation - 50 10 - 6 - +50 10 - 6 d f/f xtal(nom)(t) nominal crystal frequency deviation with temperature - 20 10 - 6 - +20 10 - 6 crystal speci?cation (x1) t amb(x1) ambient temperature 0 - 70 c c l load capacitance 8 - - pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20 % - ff c 0 parallel capacitance - 3.5 20 % - pf clock input timing (xclk) t cy cycle time 31 - 45 ns d duty factor for t llch /t llc 40 50 60 % t r rise time - - 5 ns t f fall time - - 5 ns data and control signal input timing x port, related to xclk input t su;dat input data setup time - 10 - ns t hd;dat input data hold time - 3 - ns table 240. characteristics of the digital video decoder part continued v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =0 c to 70 c (typical values measured at t amb =25 c); timings and levels refer to drawings and conditions illustrated in figure 67 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 187 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec [1] 8-bit image port output mode, expansion port is 3-stated. [2] the levels must be measured with load circuits; 1.2 k w at 3 v (ttl load); c l =50pf. [3] the effects of rise and fall times are included in the calculation of t ohd;dat and t pd . timings and levels refer to drawings and conditions illustrated in figure 67 . [4] the crystal oscillator drive level is typically 0.28 mw. clock output timing c l output load capacitance 15 - 50 pf t cy cycle time 35 - 39 ns d duty factor for t xclkh /t xclkl 35 - 65 % t r rise time 0.6 v to 2.6 v - - 5 ns t f fall time 2.6 v to 0.6 v - - 5 ns data and control signal output timing x port, related to xclk output (for xpck[1:0] 83h[5:4] = 00 is default) [3] c l output load capacitance 15 - 50 pf t ohd;dat output hold time c l =15pf - 14 - ns t pd propagation delay from positive edge of xclk output c l =15pf - 24 - ns control signal output timing rt port, related to llc output c l output load capacitance 15 - 50 pf t ohd;dat output hold time c l =15pf - 14 - ns t pd propagation delay from positive edge of llc output c l =15pf - 24 - ns iclk output timing c l output load capacitance 15 - 50 pf t cy cycle time 31 - 45 ns d duty factor for t iclkh /t iclkl 35 - 65 % t r rise time 0.6 v to 2.6 v - - 5 ns t f fall time 2.6 v to 0.6 v - - 5 ns data and control signal output timing i port, related to iclk output (for ipck[1:0] 87h[5:4] = 00 is default) c l output load capacitance at all outputs 15 - 50 pf t ohd;dat output data hold time c l =15pf - 12 - ns t o(d) output delay time c l =15pf - 22 - ns iclk input timing t cy cycle time 31 - 100 ns table 240. characteristics of the digital video decoder part continued v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =0 c to 70 c (typical values measured at t amb =25 c); timings and levels refer to drawings and conditions illustrated in figure 67 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 188 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 16. timing 16.1 digital video encoder part fig 63. input/output timing speci?cation fig 64. horizontal input timing pixclko pixclki pdn any output t d(clkd) t high t f t r v oh 0.5v dd(dvo) v ol t hd;dat t hd;dat t o(h) t o(d) t su;dat t su;dat t pixclk mbl789 v ih 0.5v dd(dvo) v il v oh v ol v ih v il hsvgc pd cbo xofs idel xpix hlen mhb905
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 189 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 16.1.1 teletext timing time t fd is the time needed to interpolate input data ttx and insert it into the cvbs and vbs output signal, such that it appears at t ttx = 9.78 m s (pal) or t ttx = 10.5 m s (ntsc) after the leading edge of the horizontal synchronization pulse. time t pd is the pipeline delay time introduced by the source that is gated by ttxrq_xclko2 in order to deliver ttx data. this delay is programmable by register ttxhd. for every active high state at output pin ttxrq_xclko2, a new teletext bit must be provided by the source. since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable (ttxhs and ttxhd), the ttx data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. time t i(ttxw) is the internally used insertion window for ttx data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 mbit/s (pal), 296 teletext bits at a text data rate of 5.7272 mbit/s (world standard ttx) or 288 teletext bits at a text data rate of 5.7272 mbit/s (nabts). the insertion window is not opened if the control bit ttxen is zero. using appropriate programming, all suitable lines of the odd ?eld (ttxovs and ttxove) plus all suitable lines of the even ?eld (ttxevs and ttxeve) can be used for teletext insertion. it is essential to note that the two pins used for teletext insertion must be con?gured for this purpose by the correct i 2 c-bus register settings . fig 65. vertical input timing hsvgc vsvgc cbo yofs ypix mhb906
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 190 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 66. teletext timing t i(ttxw) t ttx t pd t fd cvbs/y ttx_sres ttxrq_xclko2 text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mhb891
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 191 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 16.2 digital video decoder part fig 67. data input/output timing diagram (x port, rt port and i port) mhb735 t xclkh t r t r t f t hd;dat t su;dat t su;dat t hd;dat t cy t x(i)clkh t x(i)clkl t f clock input xclk data and control inputs (x port) data and control outputs x port, i port clock outputs llc, llc2, xclk, iclk and iclk input input xdq 2.4 v 1.5 v 0.6 v 2.6 v 1.5 v 0.6 v 2.0 v 0.8 v t ohd;dat t o(d) 2.4 v 0.6 v 2.0 v 0.8 v not valid
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 192 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 17. application information fig 68. application circuit (decoder part) mbl790 y1 24.576 mhz SAA7108AE saa7109ae l3 m1 m2 n1 k2 k3 l1 l2 xpd3 xpd2 xpd1 xpd0 xpd7 xpd [ 0:7 ] xpd6 xpd5 xpd4 xpd3 xpd2 xpd1 xpd0 xpd7 xpd6 xpd5 xpd4 a12 c11 b11 a11 a13 d12 c12 b12 hpd3 hpd2 hpd1 hpd0 hpd7 hpd [ 0:7 ] hpd6 hpd5 hpd4 e13 d13 c13 b13 e14 d14 c14 b14 ipd3 ipd2 ipd1 ipd0 ipd7 ipd [ 0:7 ] ipd6 ipd5 ipd4 hpd3 hpd2 hpd1 hpd0 hpd7 hpd6 hpd5 hpd4 ipd3 ipd2 ipd1 ipd0 ipd7 ipd6 ipd5 ipd4 f14 h12 h14 j14 g14 f13 g12 g13 ipcon3 ipcon2 ipcon1 ipcon0 ipcon7 ipcon [ 0:7 ] ipcon6 ipcon5 ipcon4 j12 j13 k14 l14 test5 r38 33 w r37 33 w open 3pad r49 0 w 4.7 k w m14 m12 j2 test4 j1 test3 j3 test2 c10 test1 b10 test0 test5 test4 test3 test2 test1 test0 h13 n13 n12 n10 n9 n8 n7 m7 h4 h11 l6 m13 e11 k4 k11 p5 v ssad v ssad v ssad v ssad v ssad v ssed v ssed v ssed v ssed v ssid v ssid v ssid v ssxd v ssad agnd xtout c104 10 pf c103 10 pf c107 1 nf l34 10 m h p4 p3 p2 k12 audio3 audio2 audio1 audio0 audio [ 0:3 ] l13 k13 l10 rcon0 rcon1 rcon2 rcon [ 0:2 ] m5 m6 n4 bsc0 bsc1 bsc2 bsc [ 0:2 ] res llc open r47 n14 n6 tdi_d tdo_d n5 v ddp jp45 ce_dec. dgnd 24.576 mhz 32.11 mhz r12 dgnd v ddp jp43 fxtal audio2 'strapping' dxgnd r26 56 w r25 56 w r24 56 w r23 56 w r22 56 w r21 56 w 18 w c100 47 nf r19 p6 ai24 18 w c97 47 nf r17 p7 ai23 18 w c98 47 nf r16 p9 ai22 18 w c99 47 nf r18 p10 ai21 c109 47 nf p8 18 w c101 47 nf r15 p11 ai12 18 w c102 47 nf r20 p13 ai11 0 w r29 m10 aout ai24 ai23 ai22 ai21 ai2d ai12 ai11 ai1d aout c110 47 nf p12 agnd dgnd agnd agnd dgnd llc2 r27 0 w l12 r28 0 w m11 scl sda n2 m3 m4 n3 k1 l5 amxclk alrclk asclk llc2 llc resd xtoutd xtalod xtalid amclk rtco rts0 rts1 tmsd tclkd trstd ce tdid tdod sdad scld xrh xclk xdq xrdy xtri xrv igp0 iclk idq itrdy igph igp1 itri igpv xpcon3 xpcon2 xpcon1 xpcon0 xpcon [ 0:5 ] xpcon5 xpcon4 v dd (id11) v dd (if11) v dd (ij4) v dd (ij11) v dd (il4) v dd (il11) v dd (xl8) v dd (el9) v dd (el7) v dd (eg11) v dd (ed10) v dd (am9) v dd (am8) v dd (an11) n11 m9 m8 d10 g11 l7 l9 d11 f11 j4 j11 l11 l4 l8 e12 f12 v ddad v ddad v ddad v dded v dded v dded v dded v ddid v ddid v ddid v ddid v ddid v ddid v ddxd n.c. tvd 4.7 k w i 2 c-bus_adr:40h/42h r13 dgnd v ddp jp44 rcon0 'strapping'
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 193 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 69. decoupling circuit supply voltages v dd (am8) v dd (am9) v dd (an11) v dd (eg11) v dd (el9) v dd (el7) v dd (ed10) v dd (ij4) v dd (id11) v dd (if11) v dd (ij11) v dd (il11) v dd (il4) v dd (xl8) c61 100 nf c58 100 nf c57 100 nf c59 100 nf c56 100 nf c60 100 nf c50 100 nf c49 100 nf c51 100 nf c48 100 nf c52 100 nf c54 100 nf c53 100 nf c55 100 nf dxgnd dgnd agnd open ferrite l36 dgnd agnd 001aae256
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 194 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec fig 70. application circuit (encoder part) mbl784 fltr0 agnd + 3.3 v digital dgnd dgnd agnd use one capacitor for each v ddae and v ddxe 1 nf 10 pf 27 mhz 10 pf 0.1 m h 0.1 m f 0.1 m f 0.1 m f + 3.3 v analog a5 f4 c5, d5 a8 b8 a9 d4 v dd(dvo) v ddiee a6 a10, b6, b9, c9, d9 and d6 xtalie xtaloe v ddae and v ddxe 75 w 75 w agnd agnd agnd green_vbs_cvbs hsm_csync fltr1 75 w 75 w agnd agnd agnd red_cr_c_cvbs fltr2 75 w 75 w 12 w 1 k w agnd dgnd agnd agnd agnd agnd agnd agnd blue_cb_cvbs vsm dump dump rset v ssae v ssxe v ssie a7 b7 c6 c8 c7 d8 d7 SAA7108AE saa7109ae digital inputs and outputs u y u c u cvbs e4 dgnd v ssee fig 71. fltr0, fltr1 and fltr2 as shown in figure 70 mhb912 2.7 m h 120 pf c16 jp11 jp12 fin fout c10 390 pf c13 560 pf l2 2.7 m h l3 filter 1 = byp. ll act. agnd
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 195 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec a. with 3rd harmonic quartz. crystal load = 8 pf. b. with fundamental quartz. crystal load = 20 pf. c. with fundamental quartz. crystal load = 8 pf. d. with 3rd harmonic quartz. crystal load = 8 pf. e. with fundamental quartz. crystal load = 20 pf. f. with fundamental quartz. crystal load = 8 pf. g. with direct clock. h. with fundamental quartz and restricted drive level. when p drive of the internal oscillator is too high, a resistance r s can be placed in series with the output of the oscillator xtalod. note: the decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. fig 72. oscillator application for decoder part mbl796 10 pf 10 pf 32.11 mhz SAA7108AE saa7109ae p2 xtalid xtalod p3 33 pf 33 pf 32.11 mhz 15 pf 1 nf 4.7 m h 15 pf 32.11 mhz SAA7108AE saa7109ae SAA7108AE saa7109ae p2 xtalid xtalod p3 p2 xtalid xtalod p3 mbl795 15 pf 15 pf 24.576 mhz SAA7108AE saa7109ae p2 xtalid xtalod p3 39 pf 39 pf 24.576 mhz 18 pf 1 nf 4.7 m h 18 pf 24.576 mhz SAA7108AE saa7109ae SAA7108AE saa7109ae p2 xtalid xtalod p3 p2 xtalid xtalod p3 mbl794 r s n.c. clock 32.11 mhz or 24.576 mhz SAA7108AE saa7109ae SAA7108AE saa7109ae p2 xtalid xtalod p3 p2 xtalid xtalod p3
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 196 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 17.1 reconstruction ?lter figure 71 shows a possible reconstruction ?lter for the digital-to-analog converters. due to its cut-off frequency of ~ 6 mhz, it is not suitable for hdtv applications. 17.2 analog output voltages the analog output voltages are dependent on the total load (typical value 37.5 w ), the digital gain parameters and the i 2 c-bus settings of the dac reference currents (analog settings). a. with 3rd harmonic quartz. crystal load = 8 pf. b. with fundamental quartz. crystal load = 20 pf. c. with direct clock. d. with fundamental quartz and restricted drive level. when p drive of the internal oscillator is too high, a resistance r s can be placed in series with the oscillator output xtaloe. note: the decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. fig 73. oscillator application for encoder part mbl792 39 pf 39 pf 27.00 mhz 18 pf 1 nf 4.7 m h 18 pf 27.00 mhz SAA7108AE saa7109ae SAA7108AE saa7109ae a5 xtalie xtaloe a6 a5 xtalie xtaloe a6 mbl793 r s n.c. clock 27.00 mhz SAA7108AE saa7109ae SAA7108AE saa7109ae a5 xtalie xtaloe a6 a5 xtalie xtaloe a6
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 197 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec the digital output signals in front of the dacs under nominal (nominal here stands for the settings given in t ab le 66 to t ab le 73 for example a standard pal or ntsc signal) conditions occupy different conversion ranges, as indicated in t ab le 241 for a 100 100 color bar signal. by setting the reference currents of the dacs as shown in t ab le 241 , standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16h, parameter dacf = 0000b, that means the ?ne adjustment for all dacs in common is set to 0 %. if s-video output is desired, the adjustment for the c (chrominance subcarrier) output should be identical to the one for vbs (luminance plus sync) output. 17.3 suggestions for a board layout use separate ground planes for analog and digital ground. connect these planes only at one point directly under the device, by using a 0 w resistor directly at the supply stage. use separate supply lines for the analog and digital supply. place the supply decoupling capacitors close to the supply pins. use l bead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (emc). place the analog coupling (clamp) capacitors close to the analog input pins. place the analog termination resistors close to the coupling capacitors. be careful of hidden layout capacitors around the crystal application. use serial resistors in clock, sync and data lines, to avoid clock or data re?ection effects and to soften data energy. the SAA7108AE; saa7109ae crystal temperature depends on the pcb it is soldered on. for normal air?ow conditions at a maximum ambient temperature of 70 c it will be suf?cient to provide: ? pcb dimensions at least 2000 mm 2 ? pcb at least 4 layers ? at least 50 vias (connecting pcb layers) close to the chip ? metal coverage at least 60 % on at least 2 pcb layers near the chip table 241. digital output signals conversion range set/out cvbs, sync tip-to-white vbs, sync tip-to-white rgb, black-to-white digital settings see t ab le 66 to t ab le 73 see t ab le 66 to t ab le 73 see t ab le 61 digital output 1014 881 876 analog settings e.g. b dac = 1fh e.g. g dac = 1bh e.g. r dac = g dac = b dac = 0bh analog output 1.23 v (p-p) 1.00 v (p-p) 0.70 v (p-p)
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 198 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 18. test information 18.1 boundary scan test the SAA7108AE; saa7109ae has built-in logic and 2 times 5 dedicated pins to support boundary scan testing, separately for the encoder and decoder part, which allows board testing without special hardware (nails). the SAA7108AE; saa7109ae follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by nxp. the 10 special pins are test mode select (tmse and tmsd), test clock (tcke and tckd), test reset ( trst e and trstd), test data input (tdie and tdid) and test data output (tdoe and tdod), where extension e refers to the encoder part and extension d refers to the decoder part. the boundary scan test (bst) functions bypass, extest, sample, clamp and idcode are all supported; see t ab le 242 . details about the jtag bst-test can be found in the speci?cation ieee std. 1149.1 . two ?les containing the detailed boundary scan description language (bsdl) of the SAA7108AE; saa7109ae are available on request. 18.1.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard speci?es that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst e or trstd pin low. table 242. bst instructions supported by the SAA7108AE; saa7109ae instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdie (or tdid) and tdoe (or tdod) when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 199 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 18.1.2 device identi?cation codes a device identi?cation register is speci?ed in ieee std. 1149.1b-1994 . it is a 32-bit register which contains ?elds for the speci?cation of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and to determine the version number of the ics during ?eld service. when the idcode instruction is loaded into the bst instruction register, the identi?cation register will be connected between tdie (or tdid) and tdoe (or tdod) of the ic. the identi?cation register will load a component speci?c code during the capture_data_register state of the tap controller, this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identi?cation register contains 32 bits, numbered 31 to 0, where bit 31 is the most signi?cant bit (nearest to tdie or tdid) and bit 0 is the least signi?cant bit (nearest to tdoe or tdod); see figure 74 . a. SAA7108AE. b. saa7109ae. fig 74. 32 bits of identi?cation code 000 0001 0101 0111 0001 0000 0100 (0111 0001 0001 0100) nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification tdie (or tdid) tdoe (or tdod) 31 msb lsb 28 27 12 11 1 0 1 mbl786 000 0001 0101 0111 0001 0000 0101 (0111 0001 0001 0100) nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification tdie (or tdid) tdoe (or tdod) 31 msb lsb 28 27 12 11 1 0 1 mbl787
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 200 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 19. package outline fig 75. package outline sot700-1 (lbga156) 1 a 1 b a 2 unit d y e references outline version european projection issue date 01-05-11 01-11-06 iec jedec jeita mm 1.65 0.45 0.35 1.20 0.95 15.2 14.8 y 1 15.2 14.8 e 1 13 e 2 13 0.55 0.45 0.12 0.35 dimensions (mm are the original dimensions) sot700-1 mo-192 - - - - - - e 0.25 v 0.1 w 0 5 10 mm scale sot700-1 lbga156: plastic low profile ball grid array package; 156 balls; body 15 x 15 x 1.05 mm a max. a a 2 a 1 detail x y y 1 c x d e c b a a b c d e f h k g j l m n p 2468101214 135791113 ball a1 index area ball a1 index area e e e 1 b e 2 1/2 e 1/2 e a c c b ? v m ? w m
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 201 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 20. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 20.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 20.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 20.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 202 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 20.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 76 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 243 and 244 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 76 . table 243. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 244. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 203 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . msl: moisture sensitivity level fig 76. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 204 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 21. revision history table 245. revision history document id release date data sheet status change notice supersedes SAA7108AE_ saa7109ae_3 20070206 product data sheet cpcn200505019 SAA7108AE_ saa7109ae_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors ? legal texts have been adapted to the new company name where appropriate ? t ab le 4 : updated description for pin e2, pin g2, pin l12 and pin m11 ? t ab le 240 : digital outputs; low-level output voltage for clocks corrected from - 0.5 v to 0 v ? package outline changed from sot472-1 to sot700-1 SAA7108AE_ saa7109ae_2 20040629 product speci?cation - SAA7108AE_ saa7109ae_1 SAA7108AE_ saa7109ae_1 20030326 product speci?cation - -
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 205 of 208 nxp semiconductors SAA7108AE; saa7109ae hd-codec 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 22.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 22.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 22.4 licenses 22.5 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 23. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. ics with macrovision copyright protection technology this product incorporates copyright protection technology that is protected by method claims of certain u.s. patents and other intellectual property rights owned by macrovision corporation and other rights owners. use of this copyright protection technology must be authorized by macrovision corporation and is intended for home and other limited viewing uses only, unless otherwise authorized by macrovision corporation. reverse engineering or disassembly is prohibited.
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 206 of 208 continued >> nxp semiconductors SAA7108AE; saa7109ae hd-codec 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 video decoder. . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 video encoder. . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 common features . . . . . . . . . . . . . . . . . . . . . . . 4 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 ordering information . . . . . . . . . . . . . . . . . . . . . 5 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 8 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 11 8 functional description of digital video encoder part . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 reset conditions . . . . . . . . . . . . . . . . . . . . . . . 20 8.2 input formatter . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 rgb lut . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.4 cursor insertion . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 rgb y-c b -c r matrix. . . . . . . . . . . . . . . . . . . . 22 8.6 horizontal scaler . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 vertical scaler and anti-?icker ?lter . . . . . . . . . 23 8.8 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.9 border generator. . . . . . . . . . . . . . . . . . . . . . . 23 8.10 oscillator and discrete time oscillator (dto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.11 low-pass clock generation circuit (cgc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.12 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.12.1 video path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.12.2 teletext insertion and encoding (not simultaneously with real-time control). . . . . . . 25 8.12.3 video programming system (vps) encoding. 25 8.12.4 closed caption encoder . . . . . . . . . . . . . . . . . 25 8.12.5 anti-taping (SAA7108AE only) . . . . . . . . . . . . 25 8.13 rgb processor . . . . . . . . . . . . . . . . . . . . . . . . 26 8.14 triple dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.15 hd data path. . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.16 timing generator. . . . . . . . . . . . . . . . . . . . . . . 27 8.17 pattern generator for hd sync pulses. . . . . . . 28 8.18 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 power-down modes . . . . . . . . . . . . . . . . . . . . 31 8.20 programming the graphics acquisition scaler of the video encoder . . . . . . . . . . . . . . . . . . . . 31 8.20.1 tv display window . . . . . . . . . . . . . . . . . . . . . 32 8.20.2 input frame and pixel clock . . . . . . . . . . . . . . . 32 8.20.3 horizontal scaler . . . . . . . . . . . . . . . . . . . . . . 33 8.20.4 vertical scaler. . . . . . . . . . . . . . . . . . . . . . . . . 33 8.21 input levels and formats . . . . . . . . . . . . . . . . . 34 9 functional description of digital video decoder part. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.1 analog input processing. . . . . . . . . . . . . . . . . 38 9.1.2 analog control circuits . . . . . . . . . . . . . . . . . . 38 9.1.2.1 clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.2.2 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.3 chrominance and luminance processing . . . . 43 9.1.3.1 chrominance path . . . . . . . . . . . . . . . . . . . . . 44 9.1.3.2 luminance path . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.3.3 brightness contrast saturation (bcs) control and decoder output levels . . . . . . . . . 54 9.1.4 synchronization . . . . . . . . . . . . . . . . . . . . . . . 55 9.1.5 clock generation circuit . . . . . . . . . . . . . . . . . 55 9.1.6 power-on reset and ce input . . . . . . . . . . . . . 56 9.2 decoder output formatter . . . . . . . . . . . . . . . . 58 9.3 scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.3.1 acquisition control and task handling (subaddresses 80h, 90h, 91h, 94h to 9fh and c4h to cfh). . . . . . . . . . . . . . . . . . . . . . . 64 9.3.1.1 input ?eld processing . . . . . . . . . . . . . . . . . . . 65 9.3.1.2 task handling . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3.1.3 output ?eld processing . . . . . . . . . . . . . . . . . 67 9.3.2 horizontal scaling. . . . . . . . . . . . . . . . . . . . . . 68 9.3.2.1 horizontal prescaler (subaddresses a0h to a7h and d0h to d7h) . . . . . . . . . . . . . 69 9.3.2.2 horizontal ?ne scaling (variable phase delay ?lter; subaddresses a8h to afh and d8h to dfh). . . . . . . . . . . . . . . . . . . . . . . 73 9.3.3 vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . 74 9.3.3.1 line fifo buffer (subaddresses 91h, b4h and c1h, e4h) . . . . . . . . . . . . . . . . . . . . . . . . 74 9.3.3.2 vertical scaler (subaddresses b0h to bfh and e0h to efh) . . . . . . . . . . . . . . . . . . . . . . . 75 9.3.3.3 use of the vertical phase offsets . . . . . . . . . . 76 9.4 vbi data decoder and capture (subaddresses 40h to 7fh) . . . . . . . . . . . . . . 78 9.5 image port output formatter (subaddresses 84h to 87h) . . . . . . . . . . . . . . 80 9.5.1 scaler output formatter (subaddresses 93h and c3h). . . . . . . . . . . . . 80 9.5.2 video fifo (subaddress 86h) . . . . . . . . . . . . 81 9.5.3 text fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.5.4 video and text arbitration (subaddress 86h) . 82
SAA7108AE_saa7109ae_3 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 03 6 february 2007 207 of 208 continued >> nxp semiconductors SAA7108AE; saa7109ae hd-codec 9.5.5 data stream coding and reference signal generation (subaddresses 84h, 85h and 93h) 82 9.6 audio clock generation (subaddresses 30h to 3fh). . . . . . . . . . . . . . . 85 9.6.1 master audio clock . . . . . . . . . . . . . . . . . . . . . 85 9.6.2 signals asclk and alrclk . . . . . . . . . . . . . 86 9.6.3 other control signals. . . . . . . . . . . . . . . . . . . . 87 10 input/output interfaces and ports of digital video decoder part. . . . . . . . . . . . . . . . . . . . . . 87 10.1 analog terminals. . . . . . . . . . . . . . . . . . . . . . . 88 10.2 audio clock signals . . . . . . . . . . . . . . . . . . . . . 88 10.3 clock and real-time synchronization signals. . 89 10.4 video expansion port (x port). . . . . . . . . . . . . 90 10.4.1 x port con?gured as output . . . . . . . . . . . . . . 91 10.4.2 x port con?gured as input. . . . . . . . . . . . . . . . 93 10.5 image port (i port). . . . . . . . . . . . . . . . . . . . . . 94 10.6 host port for 16-bit extension of video data i/o (h port) . . . . . . . . . . . . . . . . 96 10.7 basic input and output timing diagrams for the i and x ports . . . . . . . . . . . . . . . . . . . . 96 10.7.1 i port output timing . . . . . . . . . . . . . . . . . . . . . 96 10.7.2 x port input timing. . . . . . . . . . . . . . . . . . . . . . 96 11 i 2 c-bus description . . . . . . . . . . . . . . . . . . . . . 99 11.1 digital video encoder part. . . . . . . . . . . . . . . . 99 11.1.1 i 2 c-bus format. . . . . . . . . . . . . . . . . . . . . . . . 104 11.1.2 slave receiver . . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.3 slave transmitter . . . . . . . . . . . . . . . . . . . . . . 129 11.2 digital video decoder part. . . . . . . . . . . . . . . 130 11.2.1 i 2 c-bus format. . . . . . . . . . . . . . . . . . . . . . . . 130 11.2.2 i 2 c-bus details . . . . . . . . . . . . . . . . . . . . . . . 138 11.2.2.1 subaddress 00h . . . . . . . . . . . . . . . . . . . . . . 138 11.2.2.2 subaddress 01h . . . . . . . . . . . . . . . . . . . . . . 138 11.2.2.3 subaddress 02h . . . . . . . . . . . . . . . . . . . . . . 138 11.2.2.4 subaddress 03h . . . . . . . . . . . . . . . . . . . . . . 141 11.2.2.5 subaddress 04h . . . . . . . . . . . . . . . . . . . . . . 141 11.2.2.6 subaddress 05h . . . . . . . . . . . . . . . . . . . . . . 141 11.2.2.7 subaddress 06h . . . . . . . . . . . . . . . . . . . . . . 142 11.2.2.8 subaddress 07h . . . . . . . . . . . . . . . . . . . . . . 142 11.2.2.9 subaddress 08h . . . . . . . . . . . . . . . . . . . . . . 142 11.2.2.10 subaddress 09h . . . . . . . . . . . . . . . . . . . . . . 143 11.2.2.11 subaddress 0ah . . . . . . . . . . . . . . . . . . . . . . 144 11.2.2.12 subaddress 0bh . . . . . . . . . . . . . . . . . . . . . . 145 11.2.2.13 subaddress 0ch . . . . . . . . . . . . . . . . . . . . . . 145 11.2.2.14 subaddress 0dh . . . . . . . . . . . . . . . . . . . . . . 145 11.2.2.15 subaddress 0eh . . . . . . . . . . . . . . . . . . . . . . 146 11.2.2.16 subaddress 0fh . . . . . . . . . . . . . . . . . . . . . . 147 11.2.2.17 subaddress 10h . . . . . . . . . . . . . . . . . . . . . . 147 11.2.2.18 subaddress 11h . . . . . . . . . . . . . . . . . . . . . . 147 11.2.2.19 subaddress 12h . . . . . . . . . . . . . . . . . . . . . . 148 11.2.2.20 subaddress 13h . . . . . . . . . . . . . . . . . . . . . . 150 11.2.2.21 subaddress 14h . . . . . . . . . . . . . . . . . . . . . . 151 11.2.2.22 subaddress 15h . . . . . . . . . . . . . . . . . . . . . . 151 11.2.2.23 subaddress 16h . . . . . . . . . . . . . . . . . . . . . . 152 11.2.2.24 subaddress 17h . . . . . . . . . . . . . . . . . . . . . . 152 11.2.2.25 subaddress 18h . . . . . . . . . . . . . . . . . . . . . . 152 11.2.2.26 subaddress 19h . . . . . . . . . . . . . . . . . . . . . . 153 11.2.2.27 subaddress 1fh. . . . . . . . . . . . . . . . . . . . . . 153 11.2.3 programming register audio clock generation 154 11.2.3.1 subaddresses 30h to 32h . . . . . . . . . . . . . . 154 11.2.3.2 subaddresses 34h to 36h . . . . . . . . . . . . . . 154 11.2.3.3 subaddress 38h . . . . . . . . . . . . . . . . . . . . . . 154 11.2.3.4 subaddress 39h . . . . . . . . . . . . . . . . . . . . . . 154 11.2.3.5 subaddress 3ah. . . . . . . . . . . . . . . . . . . . . . 154 11.2.4 programming register vbi data slicer. . . . . . 155 11.2.4.1 subaddress 40h . . . . . . . . . . . . . . . . . . . . . . 155 11.2.4.2 subaddresses 41h to 57h . . . . . . . . . . . . . . 155 11.2.4.3 subaddress 58h . . . . . . . . . . . . . . . . . . . . . . 156 11.2.4.4 subaddress 59h . . . . . . . . . . . . . . . . . . . . . . 156 11.2.4.5 subaddress 5ah. . . . . . . . . . . . . . . . . . . . . . 156 11.2.4.6 subaddress 5bh. . . . . . . . . . . . . . . . . . . . . . 156 11.2.4.7 subaddress 5dh . . . . . . . . . . . . . . . . . . . . . 156 11.2.4.8 subaddress 5eh. . . . . . . . . . . . . . . . . . . . . . 157 11.2.4.9 subaddress 60h . . . . . . . . . . . . . . . . . . . . . . 157 11.2.4.10 subaddresses 61h and 62h . . . . . . . . . . . . . 157 11.2.5 programming register interfaces and scaler part . . . . . . . . . . . . . . . . . . . . . . . 157 11.2.5.1 subaddress 80h . . . . . . . . . . . . . . . . . . . . . . 157 11.2.5.2 subaddresses 83h to 87h . . . . . . . . . . . . . . 158 11.2.5.3 subaddress 88h . . . . . . . . . . . . . . . . . . . . . . 162 11.2.5.4 subaddress 8fh. . . . . . . . . . . . . . . . . . . . . . 162 11.2.5.5 subaddresses 90h and c0h. . . . . . . . . . . . . 163 11.2.5.6 subaddresses 91h to 93h . . . . . . . . . . . . . . 164 11.2.5.7 subaddresses 94h to 9bh . . . . . . . . . . . . . . 167 11.2.5.8 subaddresses 9ch to 9fh . . . . . . . . . . . . . . 168 11.2.5.9 subaddresses a0h to a2h . . . . . . . . . . . . . . 169 11.2.5.10 subaddresses a4h to a6h . . . . . . . . . . . . . . 170 11.2.5.11 subaddresses a8h to aeh . . . . . . . . . . . . . . 171 11.2.5.12 subaddresses b0h to bfh . . . . . . . . . . . . . . 172 12 programming start setup of digital video decoder part. . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.1 decoder part . . . . . . . . . . . . . . . . . . . . . . . . 173 12.2 audio clock generation part . . . . . . . . . . . . . 174 12.3 data slicer and data type control part . . . . . 175 12.4 scaler and interfaces . . . . . . . . . . . . . . . . . . 176 12.4.1 trigger condition. . . . . . . . . . . . . . . . . . . . . . 177 12.4.2 maximum zoom factor . . . . . . . . . . . . . . . . . 177 12.4.3 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13 limiting values . . . . . . . . . . . . . . . . . . . . . . . 180 14 thermal characteristics . . . . . . . . . . . . . . . . 180 15 characteristics . . . . . . . . . . . . . . . . . . . . . . . 181
nxp semiconductors SAA7108AE; saa7109ae hd-codec ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 6 february 2007 document identifier: SAA7108AE_saa7109ae_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 16 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.1 digital video encoder part. . . . . . . . . . . . . . . 188 16.1.1 teletext timing . . . . . . . . . . . . . . . . . . . . . . . . 189 16.2 digital video decoder part. . . . . . . . . . . . . . . 191 17 application information. . . . . . . . . . . . . . . . . 192 17.1 reconstruction ?lter . . . . . . . . . . . . . . . . . . . 196 17.2 analog output voltages . . . . . . . . . . . . . . . . . 196 17.3 suggestions for a board layout . . . . . . . . . . . 197 18 test information . . . . . . . . . . . . . . . . . . . . . . . 198 18.1 boundary scan test. . . . . . . . . . . . . . . . . . . . 198 18.1.1 initialization of boundary scan circuit . . . . . . 198 18.1.2 device identi?cation codes . . . . . . . . . . . . . . 199 19 package outline . . . . . . . . . . . . . . . . . . . . . . . 200 20 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 20.1 introduction to soldering . . . . . . . . . . . . . . . . 201 20.2 wave and re?ow soldering . . . . . . . . . . . . . . 201 20.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 201 20.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . 202 21 revision history . . . . . . . . . . . . . . . . . . . . . . . 204 22 legal information. . . . . . . . . . . . . . . . . . . . . . 205 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 205 22.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 205 22.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 22.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23 contact information. . . . . . . . . . . . . . . . . . . . 205 24 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

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